Please inquire about the Power-up sequence of MCIMX6L3EVN10AB.
[Reference Manual] Hardware Development , Guide for i.MX 6SoloLite, Applications Processors
<Question >
Data sheet (74-75p) Table7-3 and Figure 7-2 have different notations on the power-up sequence, so we ask for confirmation.
The voltage supply sequence of the currently designed circuit is
1. VDD_SNVS (RTC_BAT/3V)
2. VDD_HIGH_IN, NVCC33_IO (+3.3V)
3. NVCC18_IO (+1.8V)
4. VDD_ARM_IN, VDD_SOC_IN, VDD_PU_IN, NVCC_1P2, NVCC_DRAM (+1.47V)
Power is supplied in the above order.
Please check if there is any problem when supplying power in the current state.
The data sheet shows the power sequence as shown below.
There is a difference in the order of the two parts. Please confirm which order is the correct order.
Table 7-3
1. VDD_SNVS_IN (3.3V)
2. VDD_ARM_IN (1.47V)
3. VDD_PU_IN, VDD_SOC_IN (1.47V)
4. VDD_HIGH_IN/NVCC33_IO (3.3V)
5. NVCC18_IO (1.8V)
6. NVCC_DRAM_IN (1.47V)
Figure 7-2
1. VDD_SNVS_IN
2. VDD_HIGH_IN, NVCC_HIGH
3. VDD_HIGH_CAP
4. NVCC_LOW
5. NVCC_PLL_OUT
6. NVCC_DRAM_IN
7. VDD_ARM_IN
8. VDD_PU_IN
9. VDD_SOC_IN
10. POR_B
NOTE Related content
VDD_ARM_IN, VDD_PU_IN add VDD_SOC_IN can startup at the same.
However, VDD_ARM_IN and VDD_PU_IN must be at their target values within 1ms of VDD_SOC_IN.
Please check the exact guide for the above.
Please reply about whether VDD_SOC_IN must be set within 1ms or what kind of problem occurs when it is applied at the same time.
