Dear Support,
I'd appreciate it if you could help in configuring an MT53E2G32D4 using the MX8QXP_C0_B0_LPDDR4_RPA_1.2GHz_v16.xlsx referred: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8QXP-DXP-DX-DDR-Register-Programming...
The dram die addressing is: BA[2:0]; R[16:0]; C[9:0]. The xml file allows 14,15,16 row addresses only. What change has to be done in the document in order to configure the dram with R[16:0].
Regards,
Valentin.