Hi all,
I'm trying to use the power-mode-switch example on a custom imx7ulp board. The BSP is based on the imx7ulp_evk BSP and has only minor modifications.
It looks like the CM4 is not properly reading the status of the CA7.
While in RUN mode I read the following registervalue for MUA.SR
root@imx7ulpleia:~# /unit_tests/memtool MUA.SR
SOC: i.MX7ULP
MUA Addr:0x41022000
MUA.SR Addr:0x41022060 Value:0x00F00201 - Use the Processor A Status Register (SR, 32-bit, read-write) to show interrupt status from the Processor B, general purpose flags , and to set dual function control-status bits.
MUA.SR.FN(0..2) :0x1
For n = {0, 1, 2} MUA Side Flag n.
MUA.SR.NMIC(3..3) :0x0
Processor A Non-Maskable-Interrupt Clear.
MUA.SR.EP(4..4) :0x0
MUA Side Event Pending.
MUA.SR.PM(5..6) :0x0
Processor B-side Power Mode.
MUA.SR.RS(7..7) :0x0
MUB Reset State.
MUA.SR.FUP(8..8) :0x0
MUA Flags Update Pending.
MUA.SR.RDIP(9..9) :0x1
Processor B Reset De-asserted Interrupt Pending.
MUA.SR.RAIP(10..10) :0x0
Processor B Reset Asserted Interrupt Pending.
MUA.SR.TEN(20..23) :0xf
For n = {0, 1, 2, 3} MUA Transmit Register n Empty.
MUA.SR.RFN(24..27) :0x0
For n = {0, 1, 2, 3} MUA Receive Register n Full.
MUA.SR.GIPN(28..31) :0x0
For n = {0, 1, 2, 3} MUA General Interrupt Request n Pending.
But on CM4 side the same register is read out as 0x00f0'0241 indicating that the system is in STOP/VLPS mode.
Only while Linux is booting I can read that the CA7 is in RUN mode with the CM4 example.
For the other commands implemented in the example only the reboot CA7 command works, other commands indicate that they can only be performed, when the CA7 is in VLLS status.
What would be the proper way to put the CA7 into VLPS / VLLS mode?
Any Idea, why I get different values for the same register from both cores?
Thanks
Klaas
