[iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses

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[iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses

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Coeus412
Contributor I

Question:  What is the maximum rising time of external GPT_CLOCK signal?

 

The Problem:

 

We are using iMX8 Nano CPU…We want to use GPT TIMER to count the pulse of external signal…we configure UART3_TXD pad (D18) as GPT1_CLK function and connect our external clock to this pin. We can see the GPT Counter count this signal. However, this only works with simulated signal with rising time about 50ns (see the below picture). When we inject the real signal with rising time about 250ns…the GPT does not count.

 

GPT Register.png

 

I use devmem2 tool to access the register directly as below:

 

  1. Set Custom Pin (0x30330248) as GPT1_CLOCK: 0x00000003
  2. Set Clk Select (0x303305E8) to select external clock which is GPT1_CLK: 0x00000001
  3. Set counter mode via Control Reg (0x302D0000): 0x000000C3
  4. Read the Counter value via Count (0x302D0024)

 

Compare the two rising edges of the two signal pulses

 

  • The Green Line is the simulated signal
  • The Mint Blue is the real signal

compare_two_risingEdge_two_signalPulses.jpg

 

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @Coeus412 

 

Please be sure that this condition is achaiving:

The GPT counter can be operated using an external clock from outside the device, and
this is the input pin used for that purpose. The external clock input (GPT_CLK) is treated
as asynchronous to the peripheral clock (ipg_clk). To ensure proper operations of GPT,
the external clock input frequency should be less than 1/4 of frequency of the peripheral
clock (ipg_clk). Hysteresis characteristics on this pad will be required because this is a
clock input.

(From reference manual 12.1.2.1 External Clock Input)

Best regards,

Salas.

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Coeus412
Contributor I

I notice when we use the simulated signal generated by another GPIO of IMX8 the GPT Counter can count correctly (even though the rising time 250ns same as real signal) …but it does not count the real signal.

I am checking the datasheet and found below block diagram (there is Sync block with ipg_clk). Does it mean the external GPT_CLK signal need to synchronize with ipg_clk?

gpt.png

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @Coeus412 

 

Please be sure that this condition is achaiving:

The GPT counter can be operated using an external clock from outside the device, and
this is the input pin used for that purpose. The external clock input (GPT_CLK) is treated
as asynchronous to the peripheral clock (ipg_clk). To ensure proper operations of GPT,
the external clock input frequency should be less than 1/4 of frequency of the peripheral
clock (ipg_clk). Hysteresis characteristics on this pad will be required because this is a
clock input.

(From reference manual 12.1.2.1 External Clock Input)

Best regards,

Salas.

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