Where can I get more information including sample code on how to interact with the L1 cache on the A9 and M4, and the L2 cache on the A9? There is very little documentation in the TRM. There is section 13 which talks a little about the M4 L1 cache, but's all. I've looked through the PL310 manual, but that is aimed more at synthesis. Specifically I'd like to know:
- How do you enable/disable the L1 cache
- How do you enable/disable the L2 cache
- How do you enable/disable D-side prefetch
- How do you enable/disable branch prediction
- Can the L1/L2 caches run without the mmu
- How are non-cacheable/write-back/write-through sections set up
I'm not using Linux for either the A9 or M4, although I have access of course to the BSP for the iMX6SX. If there is code in there for this in the BSP, can you point me the right module. Is there a good writeup (other than the ARM A9 Technical Reference Manual) describing using the CP15 registers? The documentation there is not very good - register details are pretty sparse.
