iMX6Q - DDR3 stress test failure (Query about MCIMX6Q-SMART DEVICE board (SPF-27516) )

[Siba]

Hi,

We are facing problems with DDR stress test failures on our custom IMX6Q design. We made our schematic similar to a reference design MCIMX6Q-SMART DEVICE board (SPF-27516) for iMX6 to DDR3 interfacing.  

The reference design is attached, and page#4 contains DDR3 interfacing details.

Now we have a query about the clock signal (DRAM_SDCLK) interfacing. In the reference design, a single clock enable (DRAM_SCLKE0), single ODT (DRAM_SDODT0) and single Chip select (DRAM_CS0_B) lines are used. But for clocks alone, both clock0 (DRAM_SDCLK0 & DRAM_SDCLK0_B) & clock1 (DRAM_SDCLK1 & DRAM_SDCLK1_B) are used for 4 DDR3 Ic’s. Please suggest, will it create any impact?  

Also, we would like to know how both clocks (clock0 & clock1) are enabled at the same time? Is there anything we need to take care in the firmware for this two clock approach.

Please let me know if any additional information is required. Thanks in advance.

[pengyong_zhang]

Hi, @Siba 

Suggestion you choose the GUI Stress Tool run the Stress test with your board.  NXP highly recommends executing the GUI based version for system testing and debugging.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6-7-Series-DDR-Tool-Release/ta-p/12...

 And your log show you have not tun the calibration before the stress test. Please run the calibration first. And the run the Stress test.

B.R

[pengyong_zhang]

hi, @Siba 

I think this may cause the stress test to fail.

Did you pass the calibration?

Please share the stress test fail log.

If the above two points are an issue, is there any possibility of providing the configuration work around to solve the issue?

>>> We do not have the workaround to solve this, you need to fix this problem with your HW engineer.

B.R

[Siba]

Hi @pengyong_zhang .

Yes, we done the calibration process before initiating our stress test. The log file is attached for your review.

We did the SI analysis for our layout file. Initially, the SI result failed. After that, we have enabled 60 ohms pull up resistors for all address and control lines and 40 ohms for ODT, after this implantation the SI got a Pass result.

So we are implementing the same changes on the current board, but the stress test result failed. We are observing the different results for the SI simulation and actual conditions. 

Regards,

Siba

[pengyong_zhang]

HI, @Siba 

Please design your PCB according to the requirements in the attached file.

B.R

[Siba]

Hi @pengyong_zhang,

Thanks for your reply.

As I mentioned earlier, we are facing problems with our current boards. We requested you to review our trace length report because we found some violations in our layout file. The observed points are listed below. We would like to know whether the violations below will create any issues? – Please confirm.

1. DQS0, DQS1, DQS6 & DQS7 trace lengths are longer than their respective clock signals.
2. Address/CMD/CTRL signals wrt clock skew is ~44 mils. But the Spec is +/-25 mils.

If the above two points are an issue, is there any possibility of providing the configuration work around to solve the issue?

Thanks, Siba

[pengyong_zhang]

Hi, @Siba 

Please use the DDR Stress Tool generate the timing.c fille for your DDR. You can download the relate resource follow the below link:

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6-7-Series-DDR-Tool-Release/ta-p/12...

B.R

[Siba]

Hi @pengyong_zhang,

Thanks for your reply,

We would like you to verify our hardware as well. The trace length report is attached for you review. In our design, the iMX6 Circuit ID is U3, and the DDR3 circuit IDs are U4, U5, U6 & U7. Our interfacing is similar to the NXP reference design.

Can you please verify the trace length between the DDR3 pins and imX6 pins and confirm which is available in accordance with the spec? We are looking for a reply at earliest.

Regards

Siba

[Siba]

Hi @pengyong_zhang 

We are not used RPA file.  Instead of RPA file we used the below register settings:

Register Address	Value Used
0x020e05a8	0x00000030
0x020e05b0	0x00000030
0x020e0524	0x00000030
0x020e051c	0x00000030
0x020e0518	0x00000030
0x020e050c	0x00000030
0x020e05b8	0x00000030
0x020e05c0	0x00000030
0x020e05ac	0x00020030
0x020e05b4	0x00020030
0x020e0528	0x00020030
0x020e0520	0x00020030
0x020e0514	0x00020030
0x020e0510	0x00020030
0x020e05bc	0x00020030
0x020e05c4	0x00020030
0x020e056c	0x00020030
0x020e0578	0x00020030
0x020e0588	0x00020030
0x020e0594	0x00020030
0x020e057c	0x00020030
0x020e0590	0x00003000
0x020e0598	0x00003000
0x020e058c	0x00000000
0x020e059c	0x00003030
0x020e05a0	0x00003030
0x020e0784	0x00000030
0x020e0788	0x00000030
0x020e0794	0x00000030
0x020e079c	0x00000030
0x020e07a0	0x00000030
0x020e07a4	0x00000030
0x020e07a8	0x00000030
0x020e0748	0x00000030
0x020e074c	0x00000030
0x020e0750	0x00020000
0x020e0758	0x00000000
0x020e0774	0x00020000
0x020e078c	0x00000030
0x020e0798	0x000C0000
0x021b0404	0x00011006
0x021b081c	0x33333333
0x021b0820	0x33333333
0x021b0824	0x33333333
0x021b0828	0x33333333
0x021b481c	0x33333333
0x021b4820	0x33333333
0x021b4824	0x33333333
0x021b4828	0x33333333
0x021b0018	0x00011740
0x021b001c	0x00008000
0x021b000c	0x898E7953
0x021b0010	0xB7328F64
0x021b0014	0x01FF00DB
0x021b002c	0x000026D2
0x021b0030	0x008E1023
0x021b0008	0x09444040
0x021b0004	0x00025576
0x021b0040	0x00000047
0x021b0000	0x841A0000
0x021b001c	0x02088032
0x021b001c	0x0208803a
0x021b001c	0x00008033
0x021b001c	0x0000803B
0x021b001c	0x00048031
0x021b001c	0x00048039
0x021b001c	0x19208030
0x021b001c	0x19208038
0x021b001c	0x04008040
0x021b001c	0x04008048
0x021b0800	0xa1390003
0x021b4800	0xA1380003
0x021b0020	0x00007800
0x021b0818	0x00022227
0x021b4818	0x00022227
0x021b083c	0x02480250
0x021b0840	0x02380238
0x021b483c	0x02400244
0x021b4840	0x02440230
0x021b0848	0x3E34363A
0x021b4848	0x3A3A3E3A
0x021b0850	0x3A3C423A
0x021b4850	0x48254A36
0x021b080c	0x0005000D
0x021b0810	0x001A0017
0x021b480c	0x0009001D
0x021b4810	0x0005000D
0x021b08b8	0x00000800
0x021b48b8	0x00000800
0x021b001c	0x00000000
0x021b0404	0x00011006
0x020c4068	0xFFFFFFFF
0x020c406c	0xFFFFFFFF
0x020c4070	0xFFFFFFFF
0x020c4074	0xFFFFFFFF
0x020c4078	0xFFFFFFFF
0x020c407c	0xFFFFFFFF
0x020c4080	0xFFFFFFFF
0x020c8000	0x80012053
0x020c8000	0x80012053
0x020c8000	0x80002053
0x020c4014	0x00018D40
0x020c4018	0x00062324
0x020c401c	0x00F00000

Regards,

Siba

[pengyong_zhang]

Hi, @Siba 

You can see that the DRAM_SDCLK1 & DRAM_SDCLK1_B, DRAM_SDCLK0 & DRAM_SDCLK0_B are both use the same DRAM_SDCKE0 signal, So i think both clocks (clock0 & clock1) are enabled at the same time as defalut.

And you mentioned your stress test is failed, Please share your RPA file and fail log.

B.R