I'm working with i.MX6 solo processor and I conect a LVDS panal to the board. Sometimes the LVDS clock is not generated by the processor.
I change the clock base from the default setting MMDC_CH1 clock to the pll5 clock to set the needed clock frequency.
Is there a problem with the LVDS clock generator if I change the base clock?
Can somebody help me?
Hi Beat
one can test LVDS clock with SDK and check if it is caused by
HW or SW reasons
i.MX 6Series Platform SDK : Bare-metal SDK for the i.MX 6 series
Best regards
igor
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Hello Igor
Thank you for the fast answer but I could not solve the problem.
I found the following description from Ranjani.Vaidyanathan freescale.com and fabio.estevam freescale.com:
[PATCH] ARM: imx6: Fix procedure to switch the parent of LDB_DI_CLK
I have a Windwos Embedded Compact 7 environment so I adapted the linux code to my boot code. But it's not working!
I also tried to change only the frequence of the MMDC_CH1_AXI_CLK_ROOT but without success.
Do you have contact to this person above to get more information about the behavior of the ldb_di_ipu_divider?
I can reboot the CPU between 10 to 300 times and then the ldb_di_ipu clock is not working!
Kind regards
Beat
Hi Beat
some of them working on meta-fsl-arm mailing list:
https://lists.yoctoproject.org/listinfo/meta-freescale
Best regards
igor