The processor is i.mx8mq, it seems different from i.mx8mm. see fsl_sai.txt:
Optional properties (for mx6ul):
- fsl,sai-mclk-direction-output: This is a boolean property. If present,
indicates that SAI will output the SAI MCLK clock.
and fsl_sai.c:
if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
of_device_is_compatible(np, "fsl,imx6ul-sai")) {
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
if (IS_ERR(gpr)) {
dev_err(&pdev->dev, "cannot find iomuxc registers\n");
return PTR_ERR(gpr);
}
index = of_alias_get_id(np, "sai");
if (index < 0)
return index;
regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
MCLK_DIR(index));
}
I wonder if it's possible to obtain a 512k-50M clock signal on MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK? This in is currnet used in our PCB. Or if we can obtain a proper clock from other pins, then we have to change the PCB next time.
Now we can run the codec well by feeding it's MCLK pin an external active crystal oscillator . The codec driver is simple-card and it act as DAI master.
B.R.
wen
