i.MX8ULP access pbridge2 from m33

[martinetd]

Hello,

Looking at the i.MX 8ULP architecture diagram in the imx8ulp reference manual, we can see that the PBridge2 is part of the DSP domain that is within the Real Time Domain.

I understand that the M33 core is not directly connected to the DSP domain, but I see that the crossbars (XBAR_RTD and XBAR_DSP) are connected; would it be possible to access the DSP devices from the M33 core?

When I tried to use LPSPI2 in the DPS domain I could only get the M33 core to hang/crash despite setting up the clocks as per examples/evkmimx8ulp/dsp_examples/hello_world_usart; so I assume that if it is accessible at all there must be some operation required to map the pbridge2 region in the cm33 OS.

The motivation here is that the imx8ulp has much less IO than the previous SoC we were using, and we'd like to use LPSPI2 and LPUART2 (both connected to pbridge2 in the DSP domain) from the CM33 core

Thank you,

Dominique

[Zhiming_Liu]

Hi

You need set MBC policy in  BOARD_SetTrdcGlobalConfig referring the pbridge1, using domainIdx to control which domain can access it.

.....
  /* for DMA1, USB0, USB1, ENET, UDSHC0, USDHC1, UDSHC2, CAMM Master(default domain id is 1), default TRDC
         * configuration */
        /* non secure state can access Pbridge1(MBC2_MEM1) for DMA1, USB0, USB1, ENET, UDSHC0, USDHC1, UDSHC2, CAMM
         * Master
         */
        mbcBlockConfig.memoryAccessControlSelect = TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX;
        mbcBlockConfig.nseEnable = true;    /* non secure state can access the block for DMA1, USB0, USB1, ENET, UDSHC0,
                                               USDHC1, UDSHC2, CAMM Master */
        mbcBlockConfig.mbcIdx         = 2U; /* MBC2 */
        mbcBlockConfig.domainIdx      = 1U; /* MBC2_DOM1 */
        mbcBlockConfig.slaveMemoryIdx = 1U; /* MBC2_DOM1_MEM1 */
        TRDC_GetMbcHardwareConfig(TRDC, &mbcHwConfig, mbcBlockConfig.mbcIdx, mbcBlockConfig.slaveMemoryIdx);
        for (n = 0U; n < mbcHwConfig.blockNum; n++)
        {
            mbcBlockConfig.memoryBlockIdx = n; /* MBC2_DOM1_MEM1_BLK_CFG_Wx */
            TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);
        }


....
 /* non secure state can access PCC1(PBridge1 slot 17) and ADC1(PBridge1 slot 34) for cortex-A35 */
        mbcBlockConfig.memoryAccessControlSelect = TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX;
        mbcBlockConfig.nseEnable                 = true; /* non secure state can access the block for cortex-A35 */
        mbcBlockConfig.mbcIdx                    = 2U;   /* MBC2 */
        mbcBlockConfig.domainIdx                 = 7U;   /* MBC2_DOM7 */
        mbcBlockConfig.slaveMemoryIdx            = 1U;   /* MBC2_DOM7_MEM1 */
        mbcBlockConfig.memoryBlockIdx            = 17U;  /* MBC2_DOM7_MEM1_BLK_CFG_W17 */
        TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);
        mbcBlockConfig.memoryBlockIdx = 34U;             /* MBC2_DOM7_MEM1_BLK_CFG_W34 */
        TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);

....

Best Regards
Zhiming

[martinetd]

Hello @Zhiming_Liu 

Thank you for the reply!

Checking the reference manual, in my case I want to access pbridge2 devices from the m33 so I found that MBC3 controls 18 4k blocks for Pbridge2;

(I'm not quite sure TRDC_GetMbcHardwareConfig(TRDC, &mbcHwConfig, 3, 0) (and higher slaves) all return a mbcHwConfig.blockNum=0 ; so perhaps I am missing some prerequisite? But then again it doesn't take domains so I don't think I'm understanding this properly...)

Ignoring the above and basing myself on the manual I've tried to set access to TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX + nseEnabled to all domains (domain 0-7, slave 0, block 0-2) and while that didn't seem to fail that didn't help either, my m33 program still hangs/crashes as soon as it accesses LPSPI2

(I've also removed any other reference to MBC3 I could find in board.c; and also picked a clock on Pcc2 for pbridge2 to set up as per the dsp example)

I've attached diffs that apply on top of https://github.com/NXPmicro/mcux-sdk b565979c2155efc49ffcc8cdaa1f932e19a4d0e5 and https://github.com/nxp-mcuxpresso/mcux-sdk-examples fc18ff0c12ba90fe71714eaa4244717efa18c61c

Would you happen to know what's missing?

[martinetd]

sorry for double update, patches actually attached...

[Zhiming_Liu]

Hi

There is TRDC_M33_DOMAIN_ID in board.h,  you can use it. 

            /* non secure state can access LPSPI2(T-MBC3) for M33 */
            mbcBlockConfig.memoryAccessControlSelect = TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX;
            mbcBlockConfig.nseEnable                 = true;
            mbcBlockConfig.mbcIdx                    = 3U;
            mbcBlockConfig.domainIdx                 = TRDC_M33_DOMAIN_ID;
            mbcBlockConfig.slaveMemoryIdx            = 0U;                  
           mbcBlockConfig.memoryBlockIdx = 13;
	    TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);

Referring the pdm_sai dsp demo, we need take the memoryBlockIdx from PBRIDGE2 memory map. For LPSPI2, the memoryBlockIdx should be 13

Best Regards
Zhiming

[martinetd]

Thank you for the domain name, I had missed it.

Unfortunately the m33 core still hangs when I try to send a message over LPSPI2.

I've looked a bit closer at where this hangs, and LPSPI_MasterTransferReadDataInFifoNoBuf() hangs as  LPSPI_GetStatusFlags(LPSPI2) never changes from 0.

Going earlier, at the start of LPSPI_MasterTransferBlocking() the example I'm using (examples/evkmimx8ulp/driver_examples/lpspi/polling_b2b_transfer/master) already called LPSPI_MasterInit(), so LPSPI2->CR should be 1 (enabled) but it's not; it stays at 0 even immediately after LPSPI_Enable(base, true) so I'm not sure if my problem here is with the TRDC/MBC (if it was the MBC, I'd expect any access to LPSPI2 registers to either hang or reset the controller, which it does not -- or does it just ignore anything written and always return 0 if access isn't set properly?)

Going back even further, the PCC2 memory map doesn't seem mapped?

The manual says PCC2 base address: 2810_2000h / PCC_LPSPI2 at offset 34h which should contain at least 8000_0000h if present (PR bit), but it is 0. (meanwhile PCC_LPSPI1 at 2803_00FCh contains 9200_0000h at that point)

OTOH I don't see anything explicitly mapping PCC0 (2803_0000h) either so I'm not sure what would be required here.

What do you think; am I missing something else before (or after) the TRDC settings?

Thank you.

[Zhiming_Liu]

Hi

Please add another mbcidx to map pcc2. The dsp_pdm_sai is a good example to show how to control pdm(dsp domain) from M33.

mbcBlockConfig.memoryBlockIdx = 2U;//PCC2
TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);

Best Regards
Zhiming

[daisukemizobuch]

hi @Zhiming_Liu ;

Is there any new information on this? I would be very grateful if you have any new information.

Best Regards
mizo

[Zhiming_Liu]

Hi @daisukemizobuch  @martinetd 

Let me take some time to test this.


Best Regards
Zhiming

[daisukemizobuch]

hi @Zhiming_Liu ;

Thank you. Looking forward for your response.

Best Regards
mizo

[Zhiming_Liu · Accepted solution]

Hi @daisukemizobuch 

We can't control the module resources outside of the dsp core, as I said in the other case.

Best Regards
Zhiming

[martinetd]

hi @Zhiming_Liu ;

Thank you for the reply and sorry for the slow response.

I am not sure we agree on what I am trying to do here.

The dsp_pdm_sai example (examples/evkmimx8ulp/dsp_examples/pdm_sai) certainly controls the PDM, but it does so from dsp/main_dsp.c which runs on the DSP core, and the M33 core does not do anything after starting the DSP core.

I am trying to access DSP peripherals directly from the M33 core without starting the DSP core (I do not have a license to use XCC to modify or build DSP images, so using the mailbox to control the DSP core from the M33 is not a solution either).

The dsp pdm_sai example also does not modify the TRDC (MRC/MBC) at all from the common board configuration.

I've tried adding more blocks to the TRDC Mbc without much success. I tried looking at the trdc example (examples/evkmimx8ulp/driver_examples/trdc) and it does not look like I get a fault when accessing PCC2->PCC_LPSPI2 (0x2810_2034) but LPSPI2 cannot work if that register is 0.

I have attached the patch I tried with the trdc example, here is the output I get printing PCC2->PCC_LPSPI2 (and LPSPI1 for sanity checking), after having set the MDC as you suggested (for the PCC2 block)

TRDC example start
other init
XXXXXXX LPSPI1 80000000 @ 280300fc ; LPSPI2 0 @ 28102034
Set the MRC selected memory region not accessiable
Violent MRC access at address: 0x40000000
The MRC selected region is accessiable now
Set the MBC selected memory block not accessiable
Violent MBC access at address: 0x28800000
The MBC selected block is accessiable now
TRDC example Success

It would be greatly appreciated if you could point me in the right direction.

Thank you,

Dominique