Hi,
Thanks very much for attention.
My question is to confirm if the i.MX8QM has multiple hardware reset methods. Based on my study on the circuit diagram of the i.MX 8QM CPU Card, the POR_B of the i.MX8QM only receives reset signal from PMIC.
However, I want to use an additional reset signal (not the reset signal from PMIC) to reset the i.MX8QM separately. I don't know if this solution is feasible and if it will damage the i.MX8QM chip.
According to my reset plan, I will firstly perform logical AND on the two reset signals mentioned above , and then output the result of logical AND to i.MX8QM. So, there will be two reset cases to reset i MX8QM.
The first is WD abnormality, which causes PMIC to enter WD event. PMIC will set RESETBMCU to low level and then reset i.MX8QM. At the same time, the Regulator outputs of PMIC will enter the default OTP configuration. The i.MX8QM will enter to Power On Reset.
The second is to manually reset the i.MX8QM. When I was debugging i.MX8QM, I had a requirement to reset IMX8, but I didn't want to reset i.MX8QM through PMIC. So, I set the additional reset signal to a low level to reset IMX8. In this reset situation, the Regulator output of PMIC will remain and will not enter to default OTP configuration.
I don't know if I have explained the problem clearl. And I am not sure if my second reset method is feasible, and I hope to receive your help.