i.MX8MP evk - Config Tool - ENET pin configuration

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i.MX8MP evk - Config Tool - ENET pin configuration

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Charlie_Owz
Contributor II

Hi!

Trying to put the same pin configuration from imx8mp-evk.dts to out ".mex" using Config Tool for i.MX v10, there is no way to put the following values:

https://github.com/brgl/linux/blob/master/arch/arm64/boot/dts/freescale/imx8mp-evk.dts

 

&iomuxc {
 pinctrl_fec: fecgrp {
 fsl,pins = <
 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC    0x3
 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO   0x3
 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0   0x91
 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1   0x91
 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2   0x91
 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3   0x91
 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC     0x91
 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL   0x91
 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0   0x1f
 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1   0x1f
 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2   0x1f
 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3   0x1f
 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL   0x1f
 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC   0x1f
 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02               0x19
 >;
 };

 

How can we put these values in the Config Tool v10?

 

The most approximate that we can put...

 

init_enet_pins: init_enet_pinsgrp {

fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC      0x00000006
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO     0x00000006
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0     0x00000012
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1     0x00000012
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2     0x00000012
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3     0x00000012
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK     0x00000012
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL     0x40000012
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0     0x00000016
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1     0x00000016
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2     0x00000016
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3     0x00000016
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK     0x00000016
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL     0x00000016
>;
};

 

Thanks in advanced.

 

 

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Yuri
NXP Employee
NXP Employee

@Charlie_Owz 
Hello,

  I do not think that it is possible to import Linux device tree
configuration to the i.MX Config Tool automatically. Moreover
export of the .mex file to Linux also is mainly manual procedure.
According to i.MX Config Tools User Manual, tool generated board-oriented
device tree (DTS) DTSI file is only a snippet, which contains basic device
tree elements, initial skeleton.
  Content itself may be manually merged together with existing Linux BSP
device tree file(s) in order to apply the tool generated pins configuration.

   For Your issue it is needed to define (manually) what pins are really
involved in Linux configuration and their settings, and then (manually)
configure them in the i.MX Config Tool.

From the document below:

properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.

https://github.com/brgl/linux/blob/master/Documentation/devicetree/bindings/pinctrl/fsl%2Cimx8mp-pin...

 

For example, the line

MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3

means, that SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2)
( address 0x3033_0158) is used; bit field MUX_MODE = 4 ALT4 mux port: ENET1_MDC

From .h file

#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0

https://github.com/brgl/linux/blob/master/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h

 

Regards,
Yuri.

View solution in original post

1 Reply
1,260 Views
Yuri
NXP Employee
NXP Employee

@Charlie_Owz 
Hello,

  I do not think that it is possible to import Linux device tree
configuration to the i.MX Config Tool automatically. Moreover
export of the .mex file to Linux also is mainly manual procedure.
According to i.MX Config Tools User Manual, tool generated board-oriented
device tree (DTS) DTSI file is only a snippet, which contains basic device
tree elements, initial skeleton.
  Content itself may be manually merged together with existing Linux BSP
device tree file(s) in order to apply the tool generated pins configuration.

   For Your issue it is needed to define (manually) what pins are really
involved in Linux configuration and their settings, and then (manually)
configure them in the i.MX Config Tool.

From the document below:

properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.

https://github.com/brgl/linux/blob/master/Documentation/devicetree/bindings/pinctrl/fsl%2Cimx8mp-pin...

 

For example, the line

MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3

means, that SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2)
( address 0x3033_0158) is used; bit field MUX_MODE = 4 ALT4 mux port: ENET1_MDC

From .h file

#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0

https://github.com/brgl/linux/blob/master/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h

 

Regards,
Yuri.