i.MX8MP BOOT_CFG GPIO pins assignment

[baruchsiach]

i.MX8MP Reference Manual rev1 section 6.5.2.6.1 (BOOT_MODE Pin Latching) says that GPIO pins can be used to set BOOT_CFG bits value.

I could not find anywhere in the RM the mapping of GPIO pins to BOOT_CFG signals.

Section 6.5.3 (External Signals) says:

The following table describes the external signals of SRC

But there is no following table.

Where can find the mapping for GPIO pins to BOOT_CFG signals?

Thanks,

baruch

[JorgeCas]

Hello, I hope you are doing well.

These are the GPIOs routed for boot mode function.

Best regards.

[baruchsiach]

HI JorgeCas,

Thanks for your response.

My question is about BOOT_CFG signals, not BOOT_MODE. Figure 6-32 in section 6.5.2.6.1 shows BOOT_CFG signals going to SRC_SBMR1. The text above says:

When gpio_bt_sel is set, e-fuses are used. When cleared, GPIO signals are used.

Where can I find the mapping of GPIOs to BOOT_CFG?

Thanks,

baruch

[JorgeCas]

Hello, thank you for the clarification.

Those values are taken from eFUSE settings.

This settings are described on next tables of reference manual.

• Boot eFUSE descriptions.
• NAND boot eFUSE descriptions.
• USDHC boot eFUSE descriptions.
• Serial (SPI) NOR boot eFUSE descriptions.

And the addresses are the next:

Best regards.

[baruchsiach]

Hi JorgeCas

As I mentioned in my reply an cited the documentation, eFuse are only consulted when gpio_bt_sel is set. Otherwise, GPIO signals are used instead for BOOT_CFG.

My question is which GPIO signals these are?

Thanks,

baruch

[JorgeCas]

Hello,

i.MX8MP reset sequence is as follows:

When processor is out of reset, it looks for the fuses as mentioned by you, in such case that the GPIOs are sampled, the processor maps the value of these balls:

To the BOOT_CFG values, please refer to EVK implementation:

Best regards.