i.MX7D not waking up from WFI

[matthias_schiffer]

I'm currently attempting to add some minimal power management functions to U-Boot on an i.MX7D board, but I'm having trouble to get the board to wake up from WFI, even when I disable LPM (so the core should remain in RUN mode). I don't need actual interrupt handlers, so I keep IRQs masked in CPSR.

As a minimal testcase, I've added code to U-Boot that does the following:

• Set GPC_LPCR_A7_BSC.LPM0 and LPM1 to 00 (WFI in RUN mode)
• Set GPC_LPCR_A7_BSC.IRQ_SRC_A7_WUP, IRQ_SRC_C0, IRQ_SRC_C1 to 000 (use IRQ trigger - if I understand it correctly, I don't have to set up the GIC in this configuration?)
• Unmask all IRQs in GPC_IMR*_CORE0_A7
• dsb + wfi

I have checked that there are pending IRQs in GPC_ISR*_A7, but the WFI still hangs the core "forever"; even when the GPR IRQ is set to be always pending and unmasked, the core will not stay awake. This behavior is 100% consistent.

Using a debug probe, I can stop and then continue the CPU; this will also make the execution continue after the WFI as expected (until the next WFI, where it will hang again). I have found no way to trigger the wakeup without the debug probe.

So far I've tried the following U-Boot versions, with the same results:

• Mainline-based U-Boot 2020.10
• u-boot-imx 2016.03

Do you have any suggestions what I might be missing?

[Sanket_Parekh · Accepted solution]

Hi @matthias_schiffer 

Please configure GIC for each core. I misunderstood the same question earlier.

Thanks & Regards

Sanket Parekh

[Sanket_Parekh]

Hi @matthias_schiffer 

I hope you are doing well.

Set GPC_LPCR_A7_BSC.IRQ_SRC_A7_WUP, IRQ_SRC_C0, IRQ_SRC_C1 to 000 (use IRQ trigger - if I understand it correctly, I don't have to set up the GIC in this configuration? - Yes

Please Unmask all IRQs in GPC_IMR*_CORE1_A7, and GPC_IMR*_M4.

Thanks & Regards

Sanket Parekh

[matthias_schiffer]

Hi @Sanket_Parekh 

thank you for your reply. I tried your suggestion, but unfortunately unmasking the IRQs for the other cores didn't have any effect. Note that I don't use the second A7 and the M4 core in any way, they should remain disabled.

With your suggestion applied, the contents of the GPC registers are now as follows:

303a0000: 00007ff0 00000000 80003ff0 00000000 .........?......
303a0010: 00000000 e000ff83 000000ff 00000001 ................
303a0020: 01010101 80008000 80008000 00000001 ................
303a0030: 00000000 00000000 00000000 00000000 ................
303a0040: 00000000 00000000 00000000 00000000 ................
303a0050: 00000000 00000000 00000000 00000000 ................
303a0060: 00000000 00000000 00000000 00000000 ................
303a0070: 00000011 00000000 00000000 00000000 ................
303a0080: 00000010 00000000 00000000 00000000 ................
303a0090: 00000000 00000000 00000000 00000000 ................
303a00a0: 00000000 00000000 00000000 00000000 ................
303a00b0: 00000000 00000000 00000000 00000000 ................
303a00c0: 00000000 00000000 00000000 00000000 ................
303a00d0: 00000000 00000000 00000000 00000000 ................
303a00e0: 00000000 00000000 00000000 00000041 ............A...
303a00f0: 00000000 00000000 00000000 00000000 ................

In this simple test, there are two IRQs pending: The GPR IRQ, and an ONOFF button press.