i.MX6x & interlaced video output (PAL) ?

[admin]

Hi guys,

i'm working to setting Linux configuration on iMX6D to drive by parallel RGB output a triple DAC converter for analog RGB (ADV7123), from here a AD7125 to convert analog RGB to CVBS pal format.

Until analog RGB output it's all ok and simple to set VGA output standards, but when i need a composite video output on PAL format i find problems on signal timing generation.

All it's ok on sync timing until the configuration is in "non interlaced mode", when i switch to interlaced mode (odd frame first) )the sync singnal disappear, just some spike of 100nS, but any value into sync lenght configuration does't change the output.

Here the config i'm using on Linux 3.0.35, any suggestion ?

{

  /* PAL TV output */

  "TV-PAL", 50, 720, 576, 74074,

  132, 11,

  22, 26,

  56, 9,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,

  FB_MODE_IS_DETAILED,},

[qiang_li-mpu_se]

As I know, in interlaced RGB mode, the VSYNC signal is wrong for it, it should be output from DI_PIN7 (such as IPU1_DI0_PIN7), not DI_PIN3. And you also need set the “COUNT DOWN” for DI counter 7 to enable the clock ouput. You can adjust the count down and offset value to change your VSYNC waveform, the bigger COUNT DOWN, there will be long time VSYNC keep in high. HSYNC is still output from DI_PIN2.

//This DI counter 2 is the external HSYNC clock, output from DI_PIN2.

   _ipu_di_sync_config(ipu,

     disp,   /* display */

     2,   /* counter */

     h_total - 1,  /* run count */

     DI_SYNC_CLK, /* run_resolution */

     0,   /* offset */

     DI_SYNC_NONE,  /* offset resolution */

     0,   /* repeat count */

     DI_SYNC_NONE,  /* CNT_CLR_SEL */

     1,   /* CNT_POLARITY_GEN_EN, enbale output  */

     DI_SYNC_NONE,  /* CNT_POLARITY_CLR_SEL */

     DI_SYNC_CLK,  /* CNT_POLARITY_TRIGGER_SEL, Pixel clock trigger */

     0,   /* COUNT UP */

     2*div  /* COUNT DOWN */

     );

//This DI counter 7 is the external VSYNC clock for interlaced display mode, output from DI_PIN7

   vsync_cnt = 7;

   _ipu_di_sync_config(ipu,

     disp,   /* display */

     7,   /* counter */

     v_total/2 - 1,  /* run count */

     DI_SYNC_HSYNC, /* run_resolution  */

     9,   /* offset  */

     DI_SYNC_HSYNC,  /* offset resolution */

     2,   /* repeat count */

     DI_SYNC_VSYNC,  /* CNT_CLR_SEL */

     1,   /* CNT_POLARITY_GEN_EN, enbale output */

     DI_SYNC_NONE,  /* CNT_POLARITY_CLR_SEL */

     DI_SYNC_INT_HSYNC,  /* CNT_POLARITY_TRIGGER_SEL, internal HSYNC trigger */

     0,   /* COUNT UP */

     v_sync_width  /* COUNT DOWN */

     );