i.MX6UL Available QSPI clock frequencies

[louneschibi]

When I read the reference manual ( Document Number: IMX6ULRM

Rev. 2, 03/2017 )  page 614/3619, there is a divider in the clock tree for the QSPI1_CLK_ROOT that could be used  (CSCMR1[QSPI1_PODF] ). 

The divider QSPI_PODF could only divide by 1, 2 or 8. 

Could we use other dividers such as 3, 4 , 5, or 6 or is it a mistake in the reference manual ? 

I have a doubt about that because I downloaded the NXP SDK ( Release Name: MCUXpresso Software Development Kit (SDK)

Release Version: 2.2.0 ) and in nearly all example provided for the evkimx6ul board, the value of 5(divide by 6)  is used. 

You can check the following file from the SDK for example 

./boards/evkmcimx6ul/rtos_examples/freertos_hello/clock_config_ocram.c:

CCM->CSCMR1 = (CCM->CSCMR1 & ~(CCM_CSCMR1_QSPI1_CLK_SEL_MASK | CCM_CSCMR1_QSPI1_PODF_MASK)) |  CCM_CSCMR1_QSPI1_CLK_SEL(0) | CCM_CSCMR1_QSPI1_PODF(5);

[louneschibi]

Hi Sanket Parekh, 

Thank you for your answer. I hope you will update the reference manual in the futur  

Best regards, 

Lounes CHIBI 

[Sanket_Parekh]

Hi @louneschibi 

Yes, I will raise the request for the same with the help of NXP engineering team.

Thanks & Regards

Sanket Parekh

[Sanket_Parekh · Accepted solution]

Hi @louneschibi 

I hope you are doing well.

I have discussed this query with the internal team and concluded like it is printing mistake of Reference manual. One can set the QSPI_PODF from 1 to 8.

Thanks & Regards

Sanket Parekh