i.MX6S CLKO2 does not output clock rarely when change CLKO2_DIV setting.

[satoshishimoda]

Hi community,

Our partner found a problem about i.MX6S CCM with L3.0.35_4.1.0 BSP.

Actually, they are using CLKO2 to audio master clock.

Then, they changed CLKO2_DIV setting every 10 seconds when they executed laod test.

In this case, rarely CLKO2 does not output clock after changing the divider setting.

The frequency of this problem is once for several tens of thousand times. (There is variation)

[Q1]

Would you let me know the mechanism why the CLKO2_DIV does not work well rarely?

[Q2]

Would you let me know a procedure to avoid this problem?

(e.g. stop clock source when change CLKO2_DIV setting.)

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

first it may be suggested to check if there is another

procedure/function in customer software which also changes CCM_CCOSR.

Second, one can try first to set CLKO2_EN=0 (disable CCM_CLKO2 clock),

change CLKO2_DIV, then CLKO2_EN=1 (enable CCM_CLKO2 clock).

Third, one can change CLKO2_DIV, then immediately read back CCM_CCOSR

register and compare with intended value. If it is not correct, then write CLKO2_DIV

again.

To check if misbehaviour was caused by hardware, one can try to reproduce it

on Freescale reference board with Demo images L3.0.35_4.1.0_DEMO_IMAGE_BSP :

i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux Binary Demo Files.

Best regards

igor

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