Hi community,
Our partner have a question about i.MX6DQ MMDC.
They want to know how many clock cycle the MMDC speds to send a command to a DRAM (1T or 2T).
http://www.overclockers.com/forums/showthread.php/690464-What-is-1T-2T
Would you let me know it?
And if change the number of cycles, would you let me know how change it also?
Best Regards,
Satoshi Shimoda
Hi Satoshi
seems for i.MX6DQ MMDC similar parameter would be RALAT,
defined as 5 in ddr initialization scripts for nxp reference boards.
Best regards
igor
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Dear Igor,
RALAT seems to be used for read access, not issue a command.
So I feet it is different from the 1T/2T.
I think tMRD in MMDCx_MDCFG1 register is the one.
Do you think so?
Best Regards,
Satoshi Shimoda
Hi Satoshi
to answer on that it is neceesary to know
accurate "1T/2T" definition. What document describes it ?
Also seems this parameter is from another processor
architecture, what is the reason to consider or use it
in regard to i.MX?
Best regards
igor
Dear Igor,
Please see the following documents about 1T/2T.
http://cache.freescale.com/files/32bit/doc/app_note/AN2582.pdf
http://cache.freescale.com/files/32bit/doc/app_note/AN4039.pdf
http://www.xilinx.com/Attachment/AN10706%20-%20Creating%20HyperLynx%20DDRx%20Memory%20Controller%20T...
https://www.micron.com/~/media/documents/products/technical-note/dram-modules/tn4108_ddr3_design_gui...
Our partner want the information to do signal integrity simulation.
Best Regards,
Satoshi Shimoda
http://cache.freescale.com/files/32bit/doc/app_note/AN2582.pdf
Hi Satoshi
I believe these settings are not applicable directly
to i.MX6 MMDC and there is no similar parameter for them.
Mentioned documents related to PowerQUICC memory controllers
which support memory DIMM and has such parameter in its memory controller
registers. I.MX6 memory controller MMDC has not special settings
for DIMM memories.
Regarding signal integrity simulation please use ibis model.
IBIS Model (1)
i.MX6Q|i.MX 6Quad Processors|Quad Core|NXP
Best regards
igor
Dear Igor,
OK, I understand there is no same parameter for i.MX6DQ.
So would you let me know the command length (1 cycle or 2 cycles) at least?
Best Regards,
Satoshi Shimoda
Hi Satoshi
I am not aware of cases where such kind of memory
was used with i.MX6 MMDC. As this memory is not standard
memory which could be supported by i.MX6, suggest
to escalate it with local fae or use professional services.
Note, additional support may be provided based on project
opportunity.
Best regards
igor
Dear Igor,
Sorry for my unsufficient explanation, my last question mentioned about general DDR3, not DIMM.
I understand the command length is 1 cycle to satisfy JEDEC, right?
Best Regards
Satoshi Shimoda
Hi Satoshi
could you say where in JEDEC
document is described parameter which you are
interested in. I looked at JESD79 DDR3 specs but could
not find 1T/2T parameter.
Best regards
igor
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Dear Igor,
Yes, JEDEC specification does not mentioned 1T/2T parameter as you said.
But the command length seems to be 1 cycle according to Figure 5, 6, 7, etc...
Best Regards,
Satoshi Shimoda
Hi Satoshi
"1T/2T parameter" is used by dim memories
DIMM - Wikipedia, the free encyclopedia
these modules usually are not used in i.MX6 designs,
there are no special "1T/2T' settings for them.
If you wsh to know how support them, suggest to escalate
with local fae for special support.
Best regards
igor