i.MX6 UART: reenable 9-bit slave address normal detection mode

[r_wagner]

Hi everyone,

thanks to some help from some users here, I was able to change the i.MX UART driver so that I can send and receive 9-bit frames in "slave address normal detection" mode.

Detection of the address byte (first byte) of the message is working fine.

The problem I was unable to solve to my satisfaction is "resetting" the detection.

As stated in the user manual, the address byte (9th bit = 1) and all subsequent bytes are written into the RxFIFO - this works correctly. But how should I tell the controller, that one message is completely received and it should now wait for another address byte (9th bit = 1)? 

Currently, I use the IDLE interrupt for this: When an IDLE is detected on the RX Line (after an address byte was received), then the message was received in full extent. So now, I disable the 9-bit mode (MDEN=0 to UMCR register) and directly enable 9-bit mode again (MDEN=1).

temp = readl(sport->port.membase + UMCR);
temp &= ~UMCR_MDEN; // disable 9-bit (MultiDrop) mode
writel(temp, sport->port.membase + UMCR);
temp |= UMCR_MDEN; // enable 9-bit (MultiDrop) mode
writel(temp, sport->port.membase + UMCR);

But I think this is not quite elegant.

Is there a better way to "reset" the slave address detection?

Thanks in advance

[jamesbone]

Hello,

According to the Reference Manual description of the UART SRST bit: "Reset the transmit and receive state machines,
* all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD, and UTS[6-3]"

So I think your solution it is very well.

[r_wagner]

Hi James,

thanks for your response.

My problem actually is not the resetting of the state machines, but the resetting of merely the Slave Address Detection.

[jamesbone]

You may try using the parity of the data, to switch the 9th bit.  But I think it is basically the same approach that you are doing with your implementation