i.MX6 SoloX SABRE SD - SD3 port - Unable to select NVCC_LOW

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i.MX6 SoloX SABRE SD - SD3 port - Unable to select NVCC_LOW

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daweichen
Contributor III

I have a boot image (L3.14.52 BSP) installed on SD4 port and I am trying to get a SDIO3.0 capable Wi-Fi module working on the SD3 port of an i.MX6SX SABRE SD board.  (i.e. enabling NVCC_LOW for SD3 port while boot device on SD4 port).

Here is what I did. To enable the SDIO3.0 operation, I needed SD3 port's IO voltages to be at 1.8V. So, I modified imx6sx.dtsi and imx6sx-sdb.dts files to enable the LVE bit for all SD3 pins and for three modes (default, 100-mhz, and 200-mhz).  My debug code in imx_pinconf_set() defined in pinctrl-imx.c showed the LVE bit was set during mmc/sdio card initialization for either the default or the 200-mhz mode.

After the Linux boot process had completed and user prompt became available, the SD3 port was configured for high speed, but not ultra high speed (UHS-1) as I had hoped.  I also tried L3.14.28 BSP, which produced the same result. 

I suspect this was a result of voltage levels on SD3's IO pins not reflecting the LVE-bit settings.

I did a separate experiment to verify the LVE-bit settings in booloader mode.  I modified the U-boot to set the LVE bits for the SD3 pins.  While in bootloader mode, I measured the voltage levels on the SD3 pins with a DMM and saw 3.25 volts on all pins.  (except for SD3_CLK, which had no DC voltage)  In this experiment, Wi-Fi module was not installed.  This result seems to confirm my suspicion.

I was wondering if the i.MX6 SoloX Sabre SD board could support the configuration I had - Boot image on SD4 port and a SDIO3.0 Wi-Fi module on the SD3 port.  Did I miss a step?  Suggestions?   Any feedback will be greatly appreciated.

[U-boot md command confirmed the LVE bit was set (i.e 417029)]

=> base 20e0000

Base Address: 0x020e0000

=> md 598 15

020e0598: 00417029 00417029 00417029 00417029    )pA.)pA.)pA.)pA.

020e05a8: 00417029 00417029 00417029 00417029    )pA.)pA.)pA.)pA.

020e05b8: 00417029 00417029 0001f019 0001f019    )pA.)pA.........

020e05c8: 0001f019 0001f019 0001f019 0001f019    ................

[Excerpt from Linux startup messages on the console]

mmc2: no vqmmc regulator found

mmc2: SDHCI controller on 2198000.usdhc [2198000.usdhc] using ADMA

mmc2: queuing unknown CIS tuple 0x01 (3 bytes)

mmc2: queuing unknown CIS tuple 0x1a (5 bytes)

mmc2: queuing unknown CIS tuple 0x1b (8 bytes)

mmc2: queuing unknown CIS tuple 0x14 (0 bytes)

mmc2: error -5 whilst initialising SDIO card

mmc2: queuing unknown CIS tuple 0x01 (3 bytes)

mmc2: queuing unknown CIS tuple 0x1a (5 bytes)

mmc2: queuing unknown CIS tuple 0x1b (8 bytes)

mmc2: queuing unknown CIS tuple 0x14 (0 bytes)

mmc2: queuing unknown CIS tuple 0x80 (1 bytes)

mmc2: queuing unknown CIS tuple 0x81 (1 bytes)

mmc2: new high speed SDIO card at address 0001

After a closer look at the SDHC driver code, I found out the "error -5" message was

generated because the standard tuning process required for SDR104 mode had failed.  As a result of the failure, the SDHC/SDIO initialization process reverted back to default mode - high speed mode.

[debug output from imx_pinconf_set(): The debug code outputs the register value to the console after each register update.]

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_CMD

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x59c val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_CLK

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x598 val 0x410071 readback value= 0x410071

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA0

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a0 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA1

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a4 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA2

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a8 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA3

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5ac val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA4

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b0 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA5

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b4 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA6

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b8 val 0x417069 readback value= 0x417069

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA7

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5bc val 0x417069 readback value= 0x417069

[debug output from imx_pinconf_set(): The debug code outputs the register value to the console after each register update.]

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_CMD

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x59c val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_CLK

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x598 val 0x4100f9 readback value= 0x4100f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA0

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a0 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA1

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a4 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA2

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5a8 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA3

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5ac val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA4

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b0 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA5

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b4 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA6

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5b8 val 0x4170f9 readback value= 0x4170f9

imx6sx-pinctrl 20e0000.iomuxc: pinconf set pin MX6SX_PAD_SD3_DATA7

imx6sx-pinctrl 20e0000.iomuxc: write: offset 0x5bc val 0x4170f9 readback value= 0x4170f9

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Dawei

one can check VSELECT register uSDHCx_VEND_SPEC, please

check attached 1.8V SD3 uboot example for i.MX6SL EVK.

Best regards

igor

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daweichen
Contributor III

Hi igorepadykov,

Thank you very much for your feedback.  I was able to confirm the NVCC_LOW selection in bootloader mode.    I saw 1.6 volts on SD3 pins, except for SD3 Data0 and SD3 CMD, which had 2.2V due to their respective VCC_SD3 pull-up resistors.

In lieu of applying the patch, I set the VSELECT bit in uSDHC3_VEND_SPEC register via the bootloader mw command shown below.

=> md 21980c0 10

021980c0: 20007809 00000000 00000006 00212800    .x. .........(!.

021980d0: 00000000 00000000 00000000 00000000    ................

021980e0: 00000000 00000000 00000000 00000000    ................

021980f0: 00000000 00000000 00000000 00000302    ................

=> mw 21980c0 2000780b

=> md 21980c0 10

021980c0: 2000780b 00000000 00000006 00212800    .x. .........(!.

021980d0: 00000000 00000000 00000000 00000000    ................

021980e0: 00000000 00000000 00000000 00000000    ................

021980f0: 00000000 00000000 00000000 00000302    ................

=>

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Dawei

one can check VSELECT register uSDHCx_VEND_SPEC, please

check attached 1.8V SD3 uboot example for i.MX6SL EVK.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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