i.MX6 SoloX SABRE-SD : M4 Core / U-boot Questions

[andrewwayner]

I have a few technical questions regarding the M4 core of the i.MX6 solo X core

1. I am working with the MQX 4.1.0 software for the solo X  am trying to understand whyQSPI2 address 0x78000000 is used for the start of M4 core code (i.e.  interrupt vector table). I am not seeing any explanation of this address determination in any of the Freescale documentation. Why is this starting halfway into the QSPI2 address space? Is this something specific to the actual SABRE-SD memory configuration? Please advise.
2. I am also wondering why the MQX 4.1.0 software uses 4KB of memory at address 0x2091F000 for clock management share memory. According to Figure 8-3 in section 8.4.1 of the reference manual this memory is part of the 8K stack in OCRAM used by the system boot ROM. Is there a reason why this particular memory range was needed for this function? Could it be relocated? Is it considered acceptable because the U-boot is executing when this memory is overwritten?
3. Can you please supply me with the source code for the U-boot image used to build the u-boot-sdb.imx image which is included in binary form only in the MQX 4.1.0 bundle?

[igorpadykov · Accepted solution]

Hi Andrew

1. I.MX6SX addresses can be found in Table 2-1. System memory map  IMX6SXRM

below part of i.MX_Linux_User's_Guide.pdf included in

L3.14.28_1.0.0_iMX6SX_BUNDLE

2. Usage OCRAM as memory buffer is described in sect.3.2 Running the MQX RTOS on OCRAM

Application Note How to Run the MQX RTOS on Various RAM Memories for i.MX 6SoloX (Rev.1, 05/2015)

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN5127.pdf

OCRAM usage is convenient in low power mode, when ddr is not available.

I do not think that Uboot overwrites this region.

3. please use linux sources L3.14.28_1.0.0_iMX6SX_BUNDLE

Best regards

igor

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[andrewwayner]

igor,

Thank you for this information.

However, I have follow-up questions.

1) Section 13.5 of the reference manual discusses the Cortex-M4 boot requirements. In particular it states that the A9-core is responsible for "...setting up Cortex-M4 initial exception table in TCRAML". The application note AN5127 that you referenced in your answer only specifies how to run the MQX code from QSPI (default from bundle), DDR, or OCRAM. There is no mention of how to execute code from TCRAML. This is possible right? 

2) I tried to determine what address the A9-core would use to write to the TCRAML (prior to enabling the M4 core). Table 2-1 does not specify a System memory region for accessing the TCRAML from the A9 core. There is talk about a "backdoor" access port for the A9 to write to this memory, but no description on how to do so that I could find. All my attempts to try to write to this memory have failed (doing so from the U-boot command line prompt using the "cp" command). Please advise on the correct procedure.

[igorpadykov]

HI Andrew

yes I think that it is possible to execute code from TCRAML.

For other questions I would suggest to create new thread.

Best regards

igor