i.MX6 PMIC_ON_REQ default value vs power mode "ON, first time".

[satoshishimoda]

Hi community,

I have a question about i.MX6 PMIC_ON_REQ.

Please see Table 100 in IMX6DQCEC Rev.3.

I understand PMIC_ON_REQ is default "High" logic after supply VDD_SNVS_IN since the value of out of reset condition is "Open Drain with PU (100k)", right?

Next, please see Table 60-3 in IMX6DQRM Rev.2.

If the above my understanding is correct, i.MX6DQ cannot behave as "ON, first time" in this table, can it?

Would you give me your comment whether my understanding is wrong or the "ON, first time" is unfeasible?

Best Regards,

Satoshi Shimoda

[igorpadykov]

HI Satoshi

>I understand PMIC_ON_REQ is default "High" logic after supply VDD_SNVS_IN

>since the value of out of reset condition is "Open Drain with PU (100k)", right?

Yes, right.

>Next, please see Table 60-3 in IMX6DQRM Rev.2.

>If the above my understanding is correct, i.MX6DQ cannot behave as "ON, first time" in this table, can it?

Table 60-3 describes two different cases and implies different buttons:

1. Case "Configuration with external PMIC" is saying about

"Button is pressed .. on the external PMIC". Though it is not described

in "ON, first time" - it implies "When [PMIC] button [PWRON] is pressed,

PMIC powers on. This case corresponds floating ONOFF in

Figure 60-2. Chip reset scheme under external PMIC control.

2. Case "Configuration with internal PMIC" is saying "SoC button [ONOFF] is pressed".

This case corresponds to Figure 60-1. Chip reset scheme under PMU control

Table 60-3 gives just generic PMIC usage, not exactly applicable to MMP0100.

Best regards

igor

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[satoshishimoda]

Hi Igor,

> 2. Case "Configuration with internal PMIC" is saying "SoC button [ONOFF] is pressed".

> This case corresponds to Figure 60-1. Chip reset scheme under PMU control

in this case, i.MX6 cannot satisfy the following behavior in Table 60-3 regardless of which PMIC is used because i.MX6 output PMIC_ON_REQ "1" immediately after supply VDD_SNVS_IN before pushing button, do you think so?

2. When button is pressed, 'state' goes ON, PMIC_ON_REQ goes '1'.

Best Regards,

Satoshi Shimoda

[igorpadykov]

HI Satoshi

actually on reference boards is used "Configuration with external PMIC" -

so answer is provided for this case.

Best regards

igor

[satoshishimoda]

Hi Igor,

OK, I understood your intention of your reply.

Then, let us talk in the case "Configuration with internal PMIC".

Table 60-3 says "2. When button is pressed, 'state' goes ON, PMIC_ON_REQ goes '1'", but actually PMIC_ON_REQ goes '1' before button is pressed as you replied about the default value of PMIC_ON_REQ, right?

Best Regards,

Satoshi Shimoda

[igorpadykov]

HI Satoshi

"Configuration with internal PMIC" is not used.

In general I would suggest to create new thread

for new questions.

Thanks and Best regards

igor

[satoshishimoda]

Hi Igor,

Please note that my original question is not related to SABRE board.

And my question is not changed from my original question, just changed words.

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

case "Configuration with internal PMIC" is not used all,

not in SABRE board, not other cases because

i.MX6Q is hard wired to Dumb PMIC mode.

You can find more details on internal link (please ask local FAE

to get access to it)

MX6Q DUMB_PMIC Mode Set - Dictumnet

Best regards

igor

[satoshishimoda]

Hi Igor,

> case "Configuration with internal PMIC" is not used all,

> not in SABRE board, not other cases because

> i.MX6Q is hard wired to Dumb PMIC mode.

Oh, really?

OK, I will contact to local FAE to access the link.

Best Regards,

Satoshi Shimoda