i.MX6 EIM burst write timing.

[satoshishimoda]

Hi community,

I have a question about i.MX6 EIM.

Please see chapter 22.8.7 & 22.8.8 in IMX6DQRM (Rev.2).

I can see the burst read memory access timing diagram, but not find burst "write" memory access timing diagram.

Could you send me the burst write memory access timing diagram?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

write access is the same as read with one difference: asserted EIM_WE

[EIM_RW] signal. You can refer to Figure 15 "Synchronous Memory, Write Access"

IMX6DQCEC i.MX 6Dual/6Quad Applications Processors for Consumer Products - Data Sheet

Best regards

chip

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