Hi,
I have a question about the Boot Config Fuse Over-rides which I can't seem to find a concrete answer to it.
The Boot config fuse over-rides are via the GPIO2, 3, etc... ie with external resistors most if not all are "0" at boot.
What I can't find is whether they require a pull down or whether they ony require it if the default is a '1' and we want a zero... ie can the unused BT_cfg pins be left floating and are they they pulled to GND internally? Any help!
Thanks.
DJ
So I don't need external Pull Downs on the BT_CFG Pins?
The Datasheet(s) contains information about pin state / pulling up / down.
For example, Table 101 (Signals with Differing Before Reset and After Reset States)
and Table 100 (21 x 21 mm Functional Contact Assignments) of IMX6DQCEC,
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf
Nevertheless, from Table 2-2 (EIM recommendations for developer’s boot modes)
of “Hardware Development Guide for i.MX 6 …” :
“The BOOT_CFG signals are required for proper functionality and operation
and should not be left floating. […] Note that an incorrect setting may result
from an improper booting sequence.”
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf
Have a great day,
Yuri
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Hi Yuri,
No it is still unanswered,
In relation to your comments...“The BOOT_CFG signals are required for proper functionality and operation and should not be left floating", why would you need to to pull them up or down if the IMX6DQCEC.pdf datasheet says they are pulled up e.g. one of the config pins out of reset.
EIM_DA0 L20 NVCC_EIM2 GPIO ALT0 EIM_AD00 Input PU (100K) - Boot CFG1-0
and the reply just confirms the confusion of the Config settings as per the same datasheet IMX6DQCEC.pdf
EIM_A16 H25 NVCC_EIM1 GPIO ALT0 EIM_ADDR16 Output 0 - Boot CFG0-0.
From the data sheet, the whole of CFG0-0 to 7 is an output. So how is it to be tied??? I can't pull an output high if its driving a zero unless it is an open drain!
Sorry but still unanswered.
After Reset there is a small window where there are config ports read for development reasons. The status of these CFG1 to CFG4 (i.e. whether they are pulled up or down or neither is not documented)
Regards,
DJ