i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

bikenomad · ‎07-05-2012

We have a new CPU board designed with the i.MX537 .

We're using the WEIM to talk to an FPGA, but also need to have a VGA display connected.

So we need to change the pins used for output of the HSYNC and VSYNC external signals (the QSB and Linux driver are set up to use EIM_OE and EIM_RW as the HSYNC and VSYNC output pins, but we need both of those as EIM signals instead).

Existing code outputs HSYNC and VSYNC signals on:
HSYNC: DI1_PIN7 = EIM_OE
VSYNC: DI1_PIN8 = EIM_RW

The existing code uses these counters (these names are from the OBDS code; 7 and 8 are used but not named; I added names for them):

DI_COUNTER_BASECLK 0
DI_COUNTER_IHSYNC 1
DI_COUNTER_OHSYNC 2
DI_COUNTER_OVSYNC 3 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_ALINE 4 (depends on DI_COUNTER_OHSYNC and DI_COUNTER_OVSYNC)
DI_COUNTER_ACLOCK 5 (depends on DI_COUNTER_ALINE)
(unused) 6
DI_COUNTER_OUT_HSYNC 7
DI_COUNTER_OUT_VSYNC 8 (depends on DI_COUNTER_IHSYNC)

We'd like to use these pins for HSYNC and VSYNC output:

HSYNC: DI1_PIN4 = EIM_DA15 (ALT4)
VSYNC: DI1_PIN6 = EIM_CS1 / GPIO2_24 (ALT3)

Now, since the existing code uses counter #4, I have to move the use of this counter to one of the unused counters. The remaining counters are 6, 7, and 8.

Because a counter can only refer to a counter with lower number, I have to maintain these relationships:

DI_COUNTER_OVSYNC > DI_COUNTER_IHSYNC
DI_COUNTER_ALINE > DI_COUNTER_OHSYNC
DI_COUNTER_ALINE > DI_COUNTER_OVSYNC
DI_COUNTER_ACLOCK > DI_COUNTER_ALINE
DI_COUNTER_OUT_VSYNC > DI_COUNTER_IHSYNC

So I'd like to set it up like this:
DI_COUNTER_BASECLK 0
DI_COUNTER_IHSYNC 1
DI_COUNTER_OHSYNC 2
DI_COUNTER_OVSYNC 3 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_OUT_HSYNC 4
(unused) 5
DI_COUNTER_OUT_VSYNC 6 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_ALINE 7 (depends on DI_COUNTER_OHSYNC and DI_COUNTER_OVSYNC)
DI_COUNTER_ACLOCK 8 (depends on DI_COUNTER_ALINE)

So I have to move:

DI_COUNTER_OUT_HSYNC from 7 to 4
DI_COUNTER_OUT_VSYNC from 8 to 6
DI_COUNTER_ALINE from 4 to 7
DI_COUNTER_ACLOCK from 5 to 8

I've managed to get HSYNC and VSYNC to come out the right pins by changing the setup of the DI counters, but so far have been unable to get video to come out at the same time.

One problem that I've found is that the DC template refers (I think) to a waveform generator.
The SYNC bits (low order 4 bits in the DC template microcode words) hold the number of a generator.

From the Linux code (rel_imx_2.6.35_11.09.01 tag, drivers/mxc/ipu3/ipu_disp.c, line 1487):

// _ipu_dc_write_tmpl(ipu,word,opcode,operand,map, wave, glue,sync,stop)
_ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
_ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

The WAVEFORM bits point to the DI1_DW_GEN_<i>; in this case the value written to the template is a 1 (SYNC_WAVE=0). So we're referring to DI1_DW_GEN_0.

I don't know whether the "sync" argument to _ipu_dc_write_tmpl() is actually the number of a DI waveform generator counter (that is, DI_COUNTER_ACLOCK), but when I changed my test code to refer to my new DI_COUNTER_ACLOCK (8 instead of 5), I still didn't get any output out of the R/G/B pins.

Any idea what I can do to make this work?

Thanks...

bikenomad · ‎07-27-2012

Thanks. These are the same changes I've made to my OBDS code. Did you look at the video pictures I posted?

Qiang Li said:

I also have a non-os version sample code, maybe you can compare them to find the difference.

qiang_li-mpu_se · ‎07-23-2012

I also have a non-os version sample code, maybe you can compare them to find the difference.

bikenomad · ‎07-23-2012

I said:

I tried this, and I am getting the correct sync signals. However, the video is incorrect; instead of a broad rainbow stripe (which I get when I compile and run it on the QSB), I see entirely different vertical stripes.
I'm using the OBDS code, which has a slightly different setup of the DC templates. I did, however, change the 5 to the 8 in its microcode definition.

Here are photos of what the screen should look like, and what it does look like..

vga_video-QSB.JPG is a shot of the VGA output of my test program running on the Quick Start Board. This looks like I intended it to look.
vga_video-new-target.JPG is a shot of the VGA output of my test program running on our new i.MX53 board. The sync signals are the same as on the QSB (but on different pins, as above), but the video is way different.
vga_video-new-target-detail.JPG is a detail shot of the bad video (it looks the same all the way across the screen).

My theory is that I don't have the Display Controller microcode set up right, but I'm not sure.

bikenomad · ‎07-23-2012

Thanks.

I tried this, and I am getting the correct sync signals. However, the video is incorrect; instead of a broad rainbow stripe (which I get when I compile and run it on the QSB), I see entirely different vertical stripes.

I'm using the OBDS code, which has a slightly different setup of the DC templates. I did, however, change the 5 to the 8 in its microcode definition.

FlorentAuger · ‎07-18-2012

Hi, here is what more knowledgeable colleagues suggest:

Please find below required code changes:

1.

Old:

/* Setup active data waveform to sync with DC */

_ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,

v_sync_width + v_start_width, DI_SYNC_HSYNC, height,

DI_SYNC_VSYNC, 0, DI_SYNC_NONE,

DI_SYNC_NONE, 0, 0);

New:

/* Setup active data waveform to sync with DC */

_ipu_di_sync_config(disp, 5, 0, DI_SYNC_HSYNC,

v_sync_width + v_start_width, DI_SYNC_HSYNC, height,

DI_SYNC_VSYNC, 0, DI_SYNC_NONE,

DI_SYNC_NONE, 0, 0);

2.

Old:

_ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,

h_sync_width + h_start_width, DI_SYNC_CLK,

width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,

0);

New:

_ipu_di_sync_config(disp, 8, 0, DI_SYNC_CLK,

h_sync_width + h_start_width, DI_SYNC_CLK,

width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,

0);

3.

Old:

/* set VGA delayed hsync/vsync no matter VGA enabled */

/* couter 7 for VGA delay HSYNC */

_ipu_di_sync_config(disp, 7,

h_total - 1, DI_SYNC_CLK,

18, DI_SYNC_CLK,

0, DI_SYNC_NONE,

1, DI_SYNC_NONE, DI_SYNC_CLK,

0, h_sync_width * 2);

New:

/* set VGA delayed hsync/vsync no matter VGA enabled */

/* couter 4 for VGA delay HSYNC */

_ipu_di_sync_config(disp, 4,

h_total - 1, DI_SYNC_CLK,

18, DI_SYNC_CLK,

0, DI_SYNC_NONE,

1, DI_SYNC_NONE, DI_SYNC_CLK,

0, h_sync_width * 2);

4.

Old:

/* couter 8 for VGA delay VSYNC */

_ipu_di_sync_config(disp, 8,

v_total - 1, DI_SYNC_INT_HSYNC,

1, DI_SYNC_INT_HSYNC,

0, DI_SYNC_NONE,

1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,

0, v_sync_width * 2);

New:

/* couter 6 for VGA delay VSYNC */

_ipu_di_sync_config(disp, 6,

v_total - 1, DI_SYNC_INT_HSYNC,

1, DI_SYNC_INT_HSYNC,

0, DI_SYNC_NONE,

1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,

0, v_sync_width * 2);

5.

Old:

_ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
_ipu_dc_write_tmpl(3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
_ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

New:

_ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 8, 1);
_ipu_dc_write_tmpl(3, WRG, 0, map, SYNC_WAVE, 4, 8, 1);
_ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);

bikenomad · ‎07-17-2012

Thanks, Florent.

I tried this and it still isn't working. I'm not getting any external HSYNC or VSYNC signals.

Florent Auger said:

The pin swapping described here is not valid since pin7 cannot be a source to pin8.
Instead the following pin swapping is suggested:
Pin7->Pin4
Pin8->Pin6
Pin4->Pin5
Pin5->Pin8
Please notice that wave_gen field in BSP should be updated accordingly.

Where do I do that?

I only see references to wave_gen in ipu_disp.c, as arguments to _ipu_di_data_pin_config() and _ipu_di_data_wave_config(),

but none of the calls to these functions appear to affect either non-interlaced VGA mode or the counters I'm using.

Also, the line:
_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
_ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
Should be changed to:
_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 8, 1);
_ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);

There are three lines in that section:

_ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
_ipu_dc_write_tmpl(3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
_ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

Should the 5 in all 3 of them be changed to 8, or just the last two like you showed?

qiang_li-mpu_se · ‎07-16-2012

I have a workable example in my blog,

http://imxcommunity.org/profiles/blogs/how-to-change-imx53-vga-hsync-from-di1-pin7-to-di1-pin4

It shows how to change VGA HSYNC from DI1_PIN7 to DI1_PIN4.

frankchenmh · ‎09-28-2014

Hi Li Qiang,

I have also the requirement to change the HSync and Vsync pins. I tried the link http://imxcommunity.org/profiles/blogs/how-to-change-imx53-vga-hsync-from-di1-pin7-to-di1-pin4 but it looks like the link is not correct. Could you please help update the link or re-post the artical? Thanks!

FlorentAuger · ‎07-16-2012

The pin swapping described here is not valid since pin7 cannot be a source to pin8.

Instead the following pin swapping is suggested:

Pin7->Pin4

Pin8->Pin6

Pin4->Pin5

Pin5->Pin8

Please notice that wave_gen field in BSP should be updated accordingly.

Also, the line:

_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1); _ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

Should be changed to:

_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 8, 1); _ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);

bikenomad · ‎07-10-2012

Sorry... edited the prior post to show that it's an i.MX53 (i.MX537).

FlorentAuger · ‎07-10-2012

Which i.MX are referring to?

i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

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