Hello Champs,
In the I.MX257 PDK, I breaked at 0x00000000 by JTAG and read GPIO-4 register.
It read:
DR GDIR PSR ICR1
0x53F9C000: 20000000 00000000 20000000 00000000
ICR2 IMR ISR
0x53F9C010: 00000000 00000000 DFFFFFFF 00000000
`
0x20000000 in PSR means gpio4_GPIO[29] is enabled in IOMUXC.
The corresponding DR bit is set, because it's default direction is input and data is sensed at the pad pin.
Now in the ISR, the 29 bit looks cleard
In Reference Manual, the default values of ISR is 0, however it looks 1 is the default/reset value.
Could you explain how to read ISR register?
Best regards,
Nori Shinozaki
已解决! 转到解答。
Hardly it should be a hardware to setup a mask bit : I mean normally working hardware.
But let's the customer to check the IMR setting without any software, on bare-metal board.
Regards,
Yuri.
The i.MX25 registers, in particular GPIO ones, may be changed by boot ROM,
therefore the state of some registers may be different than stated in the Reference
Manual (for just after hardware reset state). Note, JTAG debugger can be connected
to i.MX25 only after boot ROM initializations.
The GPIO interrupt status register (ISR) bits may be set because of corresponding
pin states. For example GPIO Interrupt Configuration Register(s) (ICR1, ICR2)
by default are configured for low-level sensitive ; that is if a pin state (DR, PSR) is 0
the request is set. Note, it is not possible to reset ISR while data (DR) are zero,
since events will take place again.
Have a great day,
Yuri
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Hello Yuri,
Thank you for explaining the ISR.
The issue is, my customer claims that only a GPIO3_31 bit of IMR is set by samething.
They say they are not setting it by their software.
Do you imagine any cause by hardware, pin termination, power sequence, unstable power, etc.
Best regards,
Nori Shinozaki
Hello Yuri,
I used i.MX257 EVK with JTAG to get the above result.
That is, IMRs are all 0 for each GPIOs just after out of reset.
The customer did something wrong in Software or Hardware.
He says he doesn't set the corresponding bit in his software.
Then he is asking there might be a case in hardware which set the IMR bit...
Best regards,
Nori Shinozaki