I'm struggling to find in the documentation what constraints there are to tie any of the Audio PLL's 1/2 to a SAI.TXC pin or a MCLK pin.
in the charts it looks like it is only available to mclk3 (hope not), does this mean I have to route it back physically on the board?
Hi @dav1,
Hope you are doing well.
Please accept my apologies for delay in response.
If I understood correctly, then I understood that you want to know which Audio PLL is routed to SAIx_TXC and SAIx_MCLK. Please confirm.
In addition to this, could you please let me know which chart are you referring to?
Thanks & Regards,
Ritesh M Patel
Hi @dav1,
Kindly refer to Section 14.1.1.1 SAI Master Clock Inputs/Outputs for internal clock root description in IMX8MPRM document.
For clock source selection, please refer to Slice Index 75 in Table 5-1. Clock Root Table in IMX8MPRM document.
Thanks & Regards,
Ritesh M Patel