i.MX 8M Mini/Plus PCIe PHY Internal Reference Clock Output Level Configuration

[marcelziswiler]

Despite NXP claiming otherwise, we already figured out that them reference clock signals are internally terminated so we removed our external 50 ohm resistors. However, the output level still seems rather weak, so we started looking into the reference manual concerning such configuration. Unfortunately, that part of the RM seems rather in a bad shape. Therefore our questions:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
page 3420f
CMN_REG064
Field 3
ANA_AUX_RX_TERM_GND_EN
External reference clock I/O termination to ground
0: Disable termination to GND , 1: Enable termination to GND
=> Is that where one could indeed disable the internal PCIe reference clock termination to use our external ones?

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
page 3421f
CMN_REG065
Field 3-0
ANA_AUX_TX_LVL_CTRL
TX Amplitude resistor control. Default code : 101, 375mVpp
=> However, the reset default is 1001 which is 4 bit, so what exactly are those 4 bits configuring?

=> Our preliminary testing shows a value of 1101 to give quite a satisfactory result passing the PCIe spec. What value would you recommend using?

BTW:
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
pages 3345, 3346, 3347, 3348, 3349, 3350, 3351 and 3352: [GEN1] PLL integral path charge-pump current contorl
=> control rather than contorl (16x)

BTW2:
i.MX 8M Plus Applications Processor Reference Manual, Rev. D, 12/2020
=> That one has verbatim the exact same information incl. them errors.

[marcelziswiler]

It looks like setting ANA_AUX_RX_TERM_GND_EN to zero aka disabling internal termination only works if ANA_AUX_RX_TX_SEL is set to RX and then, of course, the PCIe reference clock signals are inputs. However, we do want them to be outputs. Could you please comment on this? E.g. is it really not possible to disable the internal termination if the PCIe reference clock signals are outputs?

[igorpadykov · Accepted solution]

Please find below the input from design team:

• Regarding register ANA_AUX_RX_TERM_GND_EN - Yes, users can enable external PCIe reference clock termination to use.
• Please find below the meaning of the bitfields for CMN_REG065 - Field 3-0 (ANA_AUX_TX_LVL_CTRL): 
  

 

• Regarding the last question "setting ANA_AUX_RX_TERM_GND_EN to zero aka disabling internal termination only works if ANA_AUX_RX_TX_SEL is set to RX and then, of course, the PCIe reference clock signals are inputs. However, we do want them to be outputs. Could you please comment on this?" -> the team is not aware of a way to set the ref clock signals as outputs. Only RX mode can be available when PCIe reference clock termination is configured, so the PCIe reference clock signals are inputs.

Best regards
igor