Hi, Community!
CPU: i.MX 6ULL ( MCIMX6Y1CVK05AA / MCIMX6Y1CVK05AB ).
EIM mode: Multiplexed Address/Data Mode - 16 bit.
- 0x21B_8000 - 0x511104AF.
- 3 bit - MUM - 1 (Multiplexed Mode enable).
- 2 bit - SRD - 1 (read accesses are in Synchronous mode).
- 1 bit - SWR - 1 (write accesses are in Synchronous mode).
- 0x21B_8090 - 0x00000029.
- 3 bit - CONT_BCLK_ SEL - 1 (BCLK Continuous).
- 0 bit - BCM - 1 (The burst clock runs whenever ACLK is active).
Q1.
According to the description of the bit 3 of register 0x21B_8090 (’CONT_BCLK_SEL’) we can generate continuous clock on ‘EIM_BCLK’ output pin. However, it doesn’t. But at the same time bit 0 (’BCM’) makes it work. So what is the principal difference between these two modes? How they affect each other, e.g. when ‘CONT_BCLK_SEL’ = 1 and ‘BCM’ = 1?
Q2.
We are using FPGA in our design and ‘EIM_BCLK’ pin as a source clock for it. That’s why it is important to know if internal ‘aclk’ and external ‘EIM_BCLK’ clocks are synchronized as in i.MX6 Solo-Lite, where special DLL is used for this purpose. Interested in cases:
- Normal mode (not ‘continuous’ clock).
- Continuous clock .
- ‘BCD ≠ 0’, when ‘aclk’ > ‘EIM_BCLK’?
Q3.
Due to some limitations of the design ‘EIM_OE’ signal must be delayed for 1 cycle inside FPGA. That’s why internal FPGA scheme will hold and drive ‘A/D’ bus for 1 clock cycle longer than it is expected after transaction is finished (’EIM_CS’ and ‘EIM_OE’ deasserted).
Several experiments have been done and found that ‘A/D’ bus remains tri-stated (Z-state) between transactions. However, no official information about the state of the ‘muxed’ A/D-bus between transaction was found. So, is it safe and valid read transaction shown on the attached diagram (‘RWSC’ = 2)?
- Top diagram: ‘A/D’ bus immediately released by FPGA according to ‘EIM_OE’ signal (reference case).
- Bottom diagram: ‘A/D’ bus released by FPGA internal scheme only after additional 1 clock cycle delay (our case).
