how about Timing Diagram of imx6 read fpga via EIM in 32bit Multiplexed Address/Data mode

[roger_cheng]

Hi we are use imx6dl with fpga via EIM bus. we set up NUM=1 & DSZ=011,so we use Asynchronous and 32bit Multiplexed Address/Data mode. So my question is the read Timing Diagram is as 'Figure 22-2' page1017 (IMX6SDLRM_ Reference Manua.pdf) or as 'Figure 18. Asynchronous A/D Muxed Read Access' page 56 (IMX6SDLIEC.pdf)