clock frequency of sdio in u-boot & linux

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clock frequency of sdio in u-boot & linux

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rans
Senior Contributor I

Hello,

In linux device tree there is configuration for sdio clock-frequency:

&usdhc2 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_usdhc2_2>;

    no-1-8-v;

    bus-width = <4>;

    clock-frequency = <40000000>;

    max-frequency = <40000000>;

    keep-power-in-suspend;

    enable-sdio-wakeup;

    status = "okay";

};

But in u-boot I don't find such configuration, so I wander, how is it that u-boot can manage working with sdio in a slower rate, while linux need to be configured for that rate in device tree ?

Thank you,

Ran

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1 Solution
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igorpadykov
NXP Employee
NXP Employee

this may be due to drive strength and associated with it

signal integrity issues, in *dts file one can check for example:

        pinctrl_usdhc3: usdhc3grp {
            fsl,pins = <
                MX6QDL_PAD_SD3_CMD__SD3_CMD        0x17059
                MX6QDL_PAD_SD3_CLK__SD3_CLK        0x10059

which corresponds to register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK,

one can tweak DSE settings

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Ran

seems uboot uses rom boot usdhc settings described in

sect.8.5.3.1 Expansion Device eFUSE Configuration i.MX6DQ

Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor
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1,401 Views
rans
Senior Contributor I

Hi Igor,

Thank you,

I have a strange issue where I can access mmc from u-boot (mmc commands), but not from linux.

Not sure yet, why. It is a new board design. older design worked very well.

If the failure was both in u-boot and linux, it was easier, and we could tell is it a HW issue.

But since from u-boot is seems to work, we are not sure.

Regards,

Ran

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1,403 Views
igorpadykov
NXP Employee
NXP Employee

this may be due to drive strength and associated with it

signal integrity issues, in *dts file one can check for example:

        pinctrl_usdhc3: usdhc3grp {
            fsl,pins = <
                MX6QDL_PAD_SD3_CMD__SD3_CMD        0x17059
                MX6QDL_PAD_SD3_CLK__SD3_CLK        0x10059

which corresponds to register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK,

one can tweak DSE settings

Best regards
igor

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