Who reset IPU_CH_BUF0_RDY0/IPU_CH_BUF1_RDY0 in IMX6

[ivyliu]

Hi All,

I have a video path CSI0->SMFC->CH0->CH11->IC->CH22->CH23->DMFC->DP->DC->DI0.

But I only can get one frame displayed.

It looks like that after this display, the buffer for channel 0 and 22 are not ready.

When I mannually reset register IPU_CH_BUF0_RDY0 and IPU_CH_BUF1_RDY0 for all 4 channels, I will get another frame.

I think there is something wrong with my IPU setting.

Could someone help to explain which setting or who in IPU will clear/reset Registers IPU_CH_BUF0/1_RDY0/1 automaticaly?

Best Regards,

Ivy

[Yuri]

Hello,

  Please look at section 37.4.2.7 (AAU_W & AAU_R- Address Arithmetic
Unit for Write and Read) of i.MX6 D/Q Reference Manual about double

buffering usage. If the ARM platform is a data source for specific double-buffered
channel, it should control status of IPU buffers.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[ivyliu]

Hi Yuri,

Thank you very much!

Best Regards,

Ivy