Where to find CCM_CSCDR3 register in Linux L3.10.53

[dipalidhumal]

Hi,

We are using i.MX6DL- (MCIMX6U8DVM10AC).

We need to modify CCM_CSCDR3 register values.

Please let us know where to get this register in Linux L3.10.53 from freescale.

Please let me for more information.

Regards,

Dipali

[saurabh206]

Hi Dipali,

You can use memtool utility to modify register.

If you have yocto setup available than you can generate using bitbake imx-test.

Thanks

Saurabh

[dipalidhumal]

Hi,

We don't want to try this option with memtool utility.

We have to make it in Linux.

Please see below file and tell us the steps and procedures to be changed.

./arch/arm/mach-imx/clk-vf610.c:#define CCM_CSCDR3        (ccm_base + 0x1c)

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);

./arch/arm/mach-imx/clk-vf610.c:    clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);

Regards,

Dipali

[art]

The listing you've provided is for VF6 series Vybrid controllers platform. Try

to find the same for MX6DL platform. Also, check the corresponding device tree file:

arch/arm/boot/dts/imx6dl.dtsi

Have a great day,
Artur

[dipalidhumal]

Hi Artur,

Thanks.

We have gone through the dtsi file as you mentioned and could not find any reference to CCM_CSCDR3.

PFB listing for imx processor which is the only reference regarding this register we found in the kernel code.

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3        (MX51_CCM_BASE + 0x3C)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET        (16)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK        (0x7 << 16)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET        (9)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK        (0x3F << 9)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET        (6)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK        (0x7 << 6)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET        (0)

./arch/arm/mach-imx/crm-regs-imx5.h:#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK        (0x3F)

Is it applicable to i.MXDL? If you have more information then share it with us.

Regards,

Dipali