Use of DMA for SPI data transfer for cortex M7 of the IMX8MP

[ababatola]

Hi,

I am working on the IMX8MP platform and I am using the core M7 to copy data using the SPI from a FPGA.  I also want to use DMA for the data transfer.  After configuring my code the code did not work as I could not observe anything on my oscilloscope.

The cortex M7 is the master and the SPI is working already.  

I would like to ask if there is an example for this or if you can give me some tips for this.  I have single stepped through the code and I seems that all the DMA function calls were correctly  called and the configurations were also correct.  However, I do not get any response from the code.

What can be the problem?  The main function calls are below: -

ECSPI_MasterInit(ECSPI_MASTER_BASEADDR, &hw_src_espi::masterConfig, ECSPI_MASTER_CLK_FREQ);

SDMA_Init(ECSPI3_SDMAARM, &hw_src_dma::userConfig);

SDMA_CreateHandle(&hw_src_dma::spi_dma_handle_tx, ECSPI3_SDMAARM, TX_CHANNEL, &context_tx);

SDMA_CreateHandle(&hw_src_dma::spi_dma_handle_rx, ECSPI3_SDMAARM, RX_CHANNEL, &context_rx);

ECSPI_MasterTransferCreateHandleSDMA (ECSPI_MASTER_BASEADDR, &hw_src_dma::spi_dma_handle, dma_cbc, NULL, &hw_src_dma::spi_dma_handle_tx, &hw_src_dma::spi_dma_handle_rx, TX_EVENT_MAPPING,
RX_EVENT_MAPPING, TX_CHANNEL, RX_CHANNEL);

status_t status = ECSPI_MasterTransferSDMA (ECSPI_MASTER_BASEADDR, &hw_src_dma::spi_dma_handle, &hw_src_dma::spi_dma_xfer);
if (status == kStatus_Success)
{
PRINTF("ECSPI_MasterTransferSDMA okay. \r\n");
}

ECSPI_EnableInterrupts(ECSPI_MASTER_BASEADDR, (uint32_t)kECSPI_RxFifoReadyInterruptEnable | (uint32_t)kECSPI_TransferCompleteInterruptEnable);
ECSPI_EnableXCH(ECSPI_MASTER_BASEADDR, ECSPI_CONREG_XCH_MASK, 1);

I shall be very gratefull for a clue to solving this problem.

Thanks,

Best wishes

[Alejandro_Salas]

Hello @ababatola 

The only examples available are in the SDK folder.

You can refer to:

SDK_folder/boards/evkmimx8mp/driver_examples/sdma/memory_to_memory

and 

SDK_folder/boards/evkmimx8mp/driver_examples/ecspi

Best regards.

Salas.

[ababatola]

Hi,

Thank you for the reply.  That is what I have done but I did not get any result.  I observed that the SDMA does not get the trigger when the SPI operation is concluded.  What could be missing?

I would also like to ask if a SDMA core can be shared by the linux and the core M7.  To be precise I want to share the SDMA1 between SPI1 and SPI2 where SPI1 is controlled by the core M7 and the SPI 2 linux. Is this possible?

Thanks

[Stan88]

Hi. I also trying to activate SDMA on IMX8MP - still without success. I've tried with ECSPI, UART, QSPI - I see that all signals are OK, see callbacks and time periods looks like the data is sending - but zero on output.

Looks like SDMA doesn't work for CortexM7 here in way memory -> periphery. I don't load CortexA so it's not a problem with resources sharing. Right now i want to make some test with diff optimization level and with diff cache options.

I'll write here regardeing results later.

[Alejandro_Salas]

Hello

Also, you can try with RPMSG. Information can be found here in Linux Reference Manual.

Best regards.

Salas.

[Stan88]

Hi Salas.

I'm not sure that I understand what do you mean.

How RPMSG will help CortexM send block data via ECSPI instead of SDMA?