USDHCPAD_SETTINGS register definition

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USDHCPAD_SETTINGS register definition

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plymale_3
Contributor V

Hello,

I would like to enable the pull ups on the USDHC3 interface in the i.MX8 8M Mini to either 22K or 47K. But it looks like USDHC 3 interface is on the NAND controller and all the pins are pulled down by default. How do I change this to a pull up?  I am guessing that I need to set ENABLE_E_MMC_22K_PULLUP and USDHC_OVERIDE_PAD_SETTINGS to the correct values.  However I cannot find any description of the PAD_SETTING register.  

Where can I find a bit setting definition of the USDHCPAD_SETTINGS[7:0] register located at 0x490[31:24] in the i.MX8 8M Mini?  This register is called out in table 6-47 of the reference manual (rev 2), page 834.

Thank you for your time,

Doug

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AldoG
NXP TechSupport
NXP TechSupport

Hello,

We usually do not use this fuse if there is no need to change the pads at boot stage (ROM), it can be changed later on for example at uboot using the Pad control Register of the pad that the eMMC is connected to.

For example NAND_DATA04 is muxed to USDHC3_DATA0 so you may configure IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, you may find the description at reference manual Rev. 2 page 1556 & 1557

Best regards,
Aldo.

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