I have enabled spread spectrum on the i.MX53 for DPLL2 for EMC reasons.
This does reduce the RF emissions but I am now observing clock drift (9 seconds in 10 minutes)
Running mainline linux 3.13 or 3.16 with custom patch to configure spread spectrum.
The nominal PLL frequency is 400 MHz
The spread spectrum parameters being used are:
Toggle count = 10
According to the calculations that should give a frequency switching between 372 MHz and 428 MHz (the average being exactly 400 MHz)
So, I would not expect this to affect the system timer stability but it does:
Set time and Synchronize system and RTC:
# date -s "2014-07-31 14:11:00"; hwclock -w
Thu Jul 31 14:11:00 UTC 2014
Display initial time
# date;hwclock -r
Thu Jul 31 14:11:05 UTC 2014
Thu Jul 31 14:11:06 2014 -0.382017 seconds
Wait 10 minutes, measured from time set (so should be 14:21:00)
Re read times
# date;hwclock -r
Thu Jul 31 14:20:51 UTC 2014
Thu Jul 31 14:21:01 2014 -0.807810 seconds
So RTC has advanced 10 minutes as expected but system clock (based on i.MX53 GPT) only 9mins 51 seconds
The problem no longer occurs without spread spectrum activated.
Has anyone else tried this?
Solved! Go to Solution.
reason may be that usually from PLL2 are derived all bus/ddr clocks:
at least this is done in Freescale BSPs: L2.6.35_11_09_ER_SOURCE
That is 400MHz is allowable max. PLL2 value, since for example DDR2 max.
frequency is 400MHz, AXI_A,AXI_B - max. 400MHz (also derived from PLL2),
check Table 7-5 IMX53RM i.MX53 Reference Manual.
I am not sure about mainline linux 3.13 or 3.16 with custom patch,
but if this is so, this [PLL2 frequency switching between 372 MHz and 428 MHz]
may violate almost all processor specifications.
Another very interesting point is "SW bus frequency driver"
arch/arm/mach-mx5/bus_freq.c, description may be found in
Chapter 22 "Software Based Peripheral Domain Frequency Scaling"
This driver is also swinging bus clocks - and it assumes that nobody,
except him, is changing bus clocks.