SSI signal status of i.MX6Quad

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SSI signal status of i.MX6Quad

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t-iishii
Contributor II

Hi

I have three question about SSI module of i.MX6

 1) In Section 61.8.7 Internal Frame and Clock Shutdown, it say that

SSI will stop driving the STFS/SRFS and STCK/SRCK signals after the current
frame ends.

"SSI will stop drivint" meen that each signal will go to high-impedance state like Figure 61-25.

Is it correct?

 2) If SSI_SCR.SSIEN = 0, every I/O or Output signal state will go to Reset state in Table 61-1.

     Is this correct?

  3) Section 61.2.1 Signals Overview in imx6dq reference manual, it say that 

The Synchronous Serial Interface (SSI) can be connected directly to the external pins or
through the Digital Audio Multiplexer (AUDMUX).

But section 61.8.3 SSI Architecture, it say that 

The Synchronous Serial Interface (SSI) is connected to chip pads through the Digital
Audio Mux (AUDMUX) block.

Which one is a correct answer?

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

>Is SSI_STXD input designed to pull-up internally?

seems no, but p.695 has description:
Note that the SSI transmits a logic '1'
when its corresponding output enable is a logic '0'.

Best regards
igor

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t-iishii
Contributor II

Hi Igor,

I hope to know that if TE is disabled 4 clock cycles before the next frame,

SSI will stop  driving STXD and will become High-impedance state.

If STXD became High-impedance state by TE disable,

Please teach me a method to pull-up/down STXD line to avoid line floating status.

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

for example if STXD line is muxed on AUD3_TXD (ALT4 CSI0_DAT5),
then configure IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 with PUS=01,
PUE=1, check description in sect.36.4.395 Pad Control Register
(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05) i.MX6DQ Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor

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t-iishii
Contributor II

Hi igor

I think that pull-up register in IOMUX is work only between IOMUX and CSI0_DAT5 pin.

Because it have a output driver between AUD3_TXD and pull-up register.

IOMUX_PAD_pullup.bmp

Please see App note: Influence of Pin Setting on System Function and Performance(AN5078.pdf)

To output SSI_STXD from CSI0_DAT5 pin, it have two IP(AUDMUX and IOMUX) three module (AUD1, AUD3 and IOMUX).

   SSI                                   AUDMUX (Normal mode)                    IOMUX
+------+                  +------+--------------------------+------+            +-----+
| SSI1 |-STXD->-AUD1_TXD->| AUD1 |->Port1 TXD -> Port3 TxD->| AUD3 |->AUD3_TXD->|-|>--|->DSI0_DAT5 
+------+                  +------+--------------------------+------+            +-----+

In Section 61.8.7 of Reference manual, if SSI_SCR[TE] = 0, transmission data stops after current frame,

How to state STXD -> AUD1_TXD signal?

If it is floating state, Port1 TXD, after AUD1 signal will go to meta-stable, I think.

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

>How to state STXD -> AUD1_TXD signal?

>If it is floating state, Port1 TXD, after AUD1 signal will go to meta-stable, I think.

seems there is no way for that and you are right about meta-stable,

please check for example Figure 16-9 AUDMUX Chapter 16 i.MX6DQ RM

Best regards
igor

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t-iishii
Contributor II

Hi, igor

Thank you for your quick response.

> seems there is no way for that and you are right about meta-stable,

> please check for example Figure 16-9 AUDMUX Chapter 16 i.MX6DQ RM

In example 2 and 3, it say that 

The data lines for the SSI and Port 3 are shown. Note that the SSI transmits a logic '1'
when its corresponding output enable is a logic '0'.

And in Figure 16-9 IMX6DQRM, SSI TxD signal go to logic '1' (T1, T2, T3 state),

after data transmission(T0).

So I think that some method to tied logic '1' SSI_STXD signal.

But I can't find some setting.

Is SSI_STXD input designed to pull-up internally?

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

>Is SSI_STXD input designed to pull-up internally?

seems no, but p.695 has description:
Note that the SSI transmits a logic '1'
when its corresponding output enable is a logic '0'.

Best regards
igor

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t-iishii
Contributor II

Hi Igor

> Note that the SSI transmits a logic '1'
> when its corresponding output enable is a logic '0'.

I can show it in each network mode examples.

But I can' find in normal mode sentence.

Would you check if it is valid even in normal mode?

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

 

it is the same in normal mode

 

Best regards
igor

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t-iishii
Contributor II

Hi Igor

Thank you for your quick response.

I will ask it to my customer.

Best regards,

Ishii.

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t-iishii
Contributor II

Hi Igor

Thank you for your response.

Our customer has a noise problem.

While audio data are stopping, some noise are ride on the data line.

So, if data line will go to high-impedance after data transmit internally,

this signal is very week and will picked up a noise by nearside data line or external noise.

In section 61.8.7,  figure61-25 and 61-26 can show that FS, CLK and Data lien go to hi-z,

But sentence is not say about electrical signal status,(only "stop driving these signals").

We hope to know that electrical signal status of "stop driving" state.

Is it Hi-z? or week pull to Hi/Low?

If Hi-z, please teach me a setting of AUDMUX  or IOMUX to pull it.

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

pull can be configured using IOMUXC_SW_PAD_CTL_PAD_x_y
registers described in IOMUXC Chapter of i.MX6DQ RM

Best regards
igor

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t-iishii
Contributor II

Hello Igor,

Thank you for your quick response.

Please teach me additional two question for my understanding.

1. (no) 

In case of Figure 61-25, after TFRC status is set to 1(Frame completion State),

Each signal (CLK, FS, DATA) go to z-state

In this condition, how to state STCK, STFS, STXD off-chip block signals?

Is it keep last level of each signals?

or go to higi-impedance state?

2. (no)

In this condition, how to state STCK, STFS, STXD off-chip block signals?

Is it keep last level of each signals?

or go to higi-impedance state?

3. correct is 61.8.3

Ok. I understand that each serial signals connect only AUDMUX like a Figure 9-13.

Best regards.

Ishii

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t-iishii
Contributor II

Hi Igor,

I am sorry that my understanding is bad.

In answer 2. You say that 

"So control output states will go inactive/deasserted state."

So both STFS will go deasserted state, I understand.

How about STCK?

 If Gated clock mode, It will stop, is correct?

 If Continuous mode, clock will output continuously?

STXD

 If TE = 0, it will go to high-impedance? or go to Low level because FIFO will cleared.

By the way, are each signals (STFS, STCK STXD) show signals between SSI and

AUDMUX module?

Best regards,

Ishii.

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

STCK also will stay in inactive state (state before transmitting data).

>STXD

> If TE = 0, it will go to high-impedance? or go to Low level because FIFO will cleared.

please refer to sect.61.8.7 Internal Frame and Clock Shutdown

>By the way, are each signals (STFS, STCK STXD) show signals between SSI and

>AUDMUX module?

please refer to Figure 16-1. AUDMUX Block Diagram

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Ishii

1. no.

This is valid for disabling TE/RE case which describes sect.Section 61.8.7

2. no. As states sect.61.9.3 SSI Control Register (SSIx_SCR):

When disabled, all SSI status bits are preset to the same state
produced by the power-on reset, all control bits are unaffected,

the contents of Tx and Rx FIFOs are cleared.

So control output states will go inactive/deasserted state.

3. correct is 61.8.3 

Best regards
igor
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