SPI1 pin muxing issue

[zc_tee]

Hi all,

In my application, i need to switch the SPI1_SCLK and SPI1_MISO pin from SPI1 function to GPIO function on run time.

Below is how i do it in my driver:

#define MUX_CTL_MASK            0x07

#define _reg_SPI1_MISO_MUX_CTL  (*(VUINT32 *)IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR + 0x7C))

#define SPI1_MISO_MUX_GPIO      0x05

#define SPI1_MISO_MUX_SPI       0x02

#define _reg_SPI1_SCLK_MUX_CTL  (*(VUINT32 *)IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR + 0x74))

#define SPI1_SCLK_MUX_GPIO      0x05

#define SPI1_SCLK_MUX_SPI       0x02

void spi_pola_active_low()

{

    //set clock/data to gpio

    _reg_SPI1_MISO_MUX_CTL = (_reg_SPI1_MISO_MUX_CTL & ~MUX_CTL_MASK) | SPI1_MISO_MUX_GPIO;

    _reg_SPI1_SCLK_MUX_CTL = (_reg_SPI1_SCLK_MUX_CTL & ~MUX_CTL_MASK) | SPI1_SCLK_MUX_GPIO;

    return;

}

This implementation work successfully in i.MX6 SOLO board. However, in i.MX6 DUAL board, it fail. I am not able to toggle the SPI1_SCLK pin using normal GPIO setting. Kernel coding is the same for SOLO and DUAL board.

Is there any problem with my implementation? Appreciate some help here.

Thank you

Regards,

ZC

[igorpadykov · Accepted solution]

Hi ZC

IOMUX are different for i.MX6DQ and SoloDuaLite, please recheck Chapter 36,37

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Best regards

igor

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[zc_tee]

Hi Igor,

You are right! Thanks for the answer!