Getting VSC8502 working with iMX8QM (device tree and driver patch).
dts file changes:
#include <dt-bindings/net/mscc-phy-vsc8531.h>
...
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
clocks = <&enet1_lpcg 4>,
<&enet1_lpcg 2>,
<&enet1_lpcg 0>,
<&enet1_lpcg 1>;
phy-mode = "rgmii-rxid"; // Phy drives Rx clock. Tell Phy driver, mscc_main.c to delay clock 2 nS
phy-handle = <ðphy0>;
fsl,magic-packet;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
fsl,rgmii_txc_dly; // i.MX8 drives Tx clock. Delay Tx clock
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0630","ethernet-phy-ieee802.3-c22";
vsc8502,vddmac = <2500>;
vsc8502,edge-slowdown = <10>; // recommended for VDDMAC=2500 mV
vsc8502,led-0-mode = <VSC8531_LINK_ACTIVITY>;
vsc8502,led-1-mode = <VSC8531_LINK_10_100_ACTIVITY>;
vsc8502,led-2-mode = <VSC8531_LINK_1000_ACTIVITY>;
};
};
};
...
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M 0x06000020
IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020
IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020
IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020
IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020
IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020
IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020
IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020
IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020
IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020
IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020
IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020
IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020
IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020
>;
};
