Thanks Jaime,
To be more specific regarding my question, does the EP write access to the i.MX6 DDR memory managed by a DMA controller (for CPU core offload)?
According to Table 3-2. SDMA event mapping, in the i.MX6 i.MX 6Dual/6Quad Applications Processor Reference Manual, the PCIe is not mentioned as one of the i.MX6 DMA controller (SDMA) request signals.
Eyal
Hello,
The configuration, shown in https://community.nxp.com/docs/DOC-95014
uses IPU DMA abilities.
Have a great day,
Yuri
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