We are building a application with A53 and M4. I have read some document about RDC. Now I meet a problerm with GPIO accessing both by A53 and M4. I use GPIO3_IO11 in M4 to output a reset signal( normal high ). And use another pin from GPIO3 bank, for example GPIO3_IO22, in A53 to do other things. If no acction with GPIO3_IO22 through linux space, everything works normally in M4. But if I echo GPIO3_IO22 > /sys/class/gpio/export( pseudo-code) then GPIO3_IO11 go to low level and can not be pull up by M4. It seems M4 loss control of GPIO3_IO22. Any pin in GPIO3 bank using in linux will stop actions givien by M4.
If I use different GPIO bank in M4 and A53, GPIO1 in M4 and GPIO4 in A53, everthing goes OK.
So my question is whether this is a limitaion that the same GPIO bank can not be used both in the 2cores? was it caused by RDC? And how to solve this isse, we have a lot of plan to use the 2 core system so it's very important for us.
In my application scenario, what is the best way to aviod this conflict? Make sure the 2 cores do not use the GPIO pins in the same bank?
In the datasheet 3.2.1:
semaphore-based locking mechanism to
provide for temporary exclusivity while the domain software uses the peripheral. Once
the software of one domain has finished the task and finished with the peripheral then it
may release the semaphore making the peripheral available to the other domain.
It described a semaphore-based locking mechanism works, is this done by hardware or linux kernel or user software？
I want make sure If we have to change the schematic to let the different GPIO bank works in different CPU cores?
Wating for your response.
