Question, i.MX25 NAND boot

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Question, i.MX25 NAND boot

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1,195 次查看
Aemj
Contributor IV

Hi team,

I would like to ask about NAND boot of i.MX257.

My customer is using NAND Flash for boot device of i.MX25 on their board.

Now they are using 512Mb NAND and they plan to change it to 1Gb.

For test, they change their software and tried to boot from 1Gb NAND. And the boot failed.

The datasheet of i.MX25 says that the NAND should have address-cycle=5 and # of Blocks=62 in the case of SLC NABD with 2KB pagesize.

The specification of the 1Gb NAND Flash the customer wants to use is 4 cycles.

The customer has a concern that i.MX25 may not support such NAND(address-cycle=4).

Is it true?

The NAND is Toshiba/ TC58NVG0S3HTAI0.

Could you tell me whether the NAND meets the requirement for i.MX25 boot device?

Thanks,

Miyamoto

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886 次查看
Yuri
NXP Employee
NXP Employee

Hello,

Boot options of i.MX25 are described in app note AN3684.

http://cache.freescale.com/files/dsp/doc/app_note/AN3684.pdf

  Please refer to Table 3 (Fuse Descriptions) of the app note AN3684, regarding

using the spare size parameter :

“BT_SPARE_SIZE - Specifies the size of spare bytes for 4 Kbyte page size NAND

Flash devices.

Note: 512 byte page devices have 16 bytes spare area size,

2 Kbyte page devices have 64 bytes spare area size.

Note: Assumes that the large spare area devices (218 byte) use 8-bit ECC.

Otherwise, 4-bit ECC”.

For the TC58NVG0S3HTAI0 : page = (2K + 128) bytes and 8-bit ECC.

This means i.MX25 NFC will use only 64 bytes of spare area and 4-bit ECC.

As result, some uncorrectable errors may take place.   

As for NAND address cycles, generally it is possible to use 4 address cycles,

please refer to BT_MEM_TYPE field.  Also, please note, NAND address specifics
should be correctly reflected in secondary boot (U-boot).


Have a great day,
Yuri

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887 次查看
Yuri
NXP Employee
NXP Employee

Hello,

Boot options of i.MX25 are described in app note AN3684.

http://cache.freescale.com/files/dsp/doc/app_note/AN3684.pdf

  Please refer to Table 3 (Fuse Descriptions) of the app note AN3684, regarding

using the spare size parameter :

“BT_SPARE_SIZE - Specifies the size of spare bytes for 4 Kbyte page size NAND

Flash devices.

Note: 512 byte page devices have 16 bytes spare area size,

2 Kbyte page devices have 64 bytes spare area size.

Note: Assumes that the large spare area devices (218 byte) use 8-bit ECC.

Otherwise, 4-bit ECC”.

For the TC58NVG0S3HTAI0 : page = (2K + 128) bytes and 8-bit ECC.

This means i.MX25 NFC will use only 64 bytes of spare area and 4-bit ECC.

As result, some uncorrectable errors may take place.   

As for NAND address cycles, generally it is possible to use 4 address cycles,

please refer to BT_MEM_TYPE field.  Also, please note, NAND address specifics
should be correctly reflected in secondary boot (U-boot).


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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Aemj
Contributor IV

Hi Yuri,

Thanks a lot for your kindly comment.

You mean the NAND device, TC58NVG0S3HTAI0, can not meet the specification of i.MX25 NAND boot.

Right?

BR,

Miyamoto

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Yuri
NXP Employee
NXP Employee

Hi,

strictly speaking, yes : "TC58NVG0S3HTAI0 can not meet the specification of i.MX25 NAND boot".

Regards,

Yuri.

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Aemj
Contributor IV

Hi Yuri,

Can I understand that the NAND flash cannot be used as normal storage device, not even for boot?

Thanks,

Miyamoto

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Yuri
NXP Employee
NXP Employee

Hi,

Yes, this part cannot be used.

Regards,

Yuri.

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