i.MX6Q: How to determine IPU NPB and IPUx_SMFC_BS

[norishinozaki]

Hello Champs,

I'm capturing video from CSI and I'm wondering how to determine values for NPB and IPUx_SMFC_BS.

Could you advise how to:

- Minimize contentions at DDR from IPU and CPU master access.

- Make the best use of DDR bandwidth.

As far as I tested, the bigger the values, the more room for CPU to use DDR.

The DDR is configured in CL 8, 8 burst, 2 clock overhead, which should transfer 64byte in 14 clocks.

The CSI video input is:

640x480x3(RGB)x30(FPS)=27MB/s

Best regards,

Nori Shinozaki

[Yuri]

Hello,

  I think IPU bursts should be configured in order to provide the same
number of bytes per burst as for DDR burst. 8 or 16 pixel are  good values

for NBP.

Have a great day,
Yuri

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[norishinozaki]

Hello Yuri,

Thanks, could you confirm a concrete case.

In a case of Gray Scale 16 bit, is this correct settings?

BPP: 16

PFS: 4'h6 = Generic data

NPB: 16BPP => 1 -> 32 pixels(0x11111)

The bigger NPB and BURST_SIZE, the first the transfer rate, so we chose 32 pixels for NPB.

32 pixels(0x11111) ,3 bit right shift, then NPB[6:3] -> 0x011= BURST_SIZE

Is this correct?

But why over 32 pixels in NPB not allowed? what restriction...

Is there any parameters to improve performance?

Best regards,

Nori Shinozaki

[Yuri]

Hello,

32 pixels (64 bytes) is good choice, and consideration of "0x011= BURST_SIZE"

is correct.  The restriction of 32 pixel per burst - I think - relates to size of internal

buffer(s).

Regards,

Yuri.

[norishinozaki]

Hello Yuri,

Let me check how to get NPB and SMFC_BS values.

In the i.MX6Q SabreSD capturing from MIPI CSI,

The setting in 3.14.28 BSP is,

NPB　= 0011111 (31dec)

SMFC_BS   = 00111 (7dec)

Seems like NPB is only 2bit shifted in right.

From RM Table 37-42, it indicates,

BPP -> All other

PFS -> All other

Is this really expecting values for Sabre board?

Best regards,

Nori Shinozaki

[norishinozaki]

Hello Yuri,

Thanks always!

BR,

N.Shinozaki