HI,
We are designing a custom board using i.MX 8 DualXPlus CPU based on the i.MX 8QXP MEK board.
In order to simplify the Reset Scheme, we are doing the following changes:
1. The SCU_WDOG_OUT and PMIC_WDOG_IN is bypassed (connected directly).
2. PMIC_POR_B_1V8 is logically ANDed with the supervisory circuit as shown in the attached image:
We have two questions:
1. In the event of pressing the manual reset button SW1, it will drive MANUAL_RESET to 0V eventually driving POR_B_1V8 to 0V so that the processor resets. During this, does the PMIC also perform a reset operation ( complete power cycle of all regulators)?
2. What will be the behaviour of PMIC_ON_REQ signal from the processor in the above event?
Hi Harsh
1. in such connection PMIC will not perform a reset operation, because
PMIC is reset by PMIC_WDOG_IN signal.
2. behaviour of PMIC_ON_REQ signal will be unaffected.
Best regards
igor
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Hi Igor,
Thanks for the reply.
So if we keep the PMIC WDI signal interfacing as it is in original design:
Does this ensure a hard WD reset (reset of all voltage regulators+ reset of MCU) when we press the SW1 button?
And in the design why is R1395 kept DNP?
We are going to use the PMIC MC34PF8100FJEP.
Hi Harsh
>Does this ensure a hard WD reset (reset of all voltage regulators+ reset of MCU) when we press the SW1 button?
yes
>And in the design why is R1395 kept DNP?
PMIC_POR_B_1V8 will be produced by PMIC reset on p.8, so it is duplication.
Best regards
igor