Hi David,
Although multiple cores are available on this processor, only core0 automatically activates during the initial boot process. System Reset Controller (SRC) module, handles the reset signal for each core. By default, SRC keeps the secondary cores in a reset state after boot. Therefore, the application needs to enable the other available cores.
To enable the other available cores:
1. Initialize persistent bits for the secondary core being activated.
2. Set the core_enable signal for each of the cores in the SRC Control Register (bits 22:24, for core1, core2, and core3 respectively).
3. Once the enable bits are set, the corresponding core is released from its reset state, and it executes the boot ROM (at 0000 0000h).
4. The boot ROM determines if it is a secondary core and uses the presistent bit registers to determine what to execute next.
This boot process is described in detail in the "System Boot" chapter of the reference
manual.
Regards,
Carlos
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