Max frequency of ARM_CLK_ROOT in i.MX6DQ for automotive.

[keitanagashima]

Dear Sir or Madam,

Hello.

Refer to "18.3 CCM Clock Tree" in IMX6DQRM_Rev.2.

There is below description.

"The default frequency values (in MHz) for the PLLs and PFDs is the maximum allowed frequency. The PLL and PFD control registers should not be programmed to exceed these values."

Next, refer to "Table 18-4. System Clock Frequency Values".

ARM_CLK_ROOT Default Frequency was 792MHz.

freescale has i.MX6DQ product for automotive with 1 GHz grade.

What description is right?

Please give me the correct CCM tree.

(If the RM was typo, please fix these description)

Best Regards,

Keita

[igorpadykov · Accepted solution]

Hi Keita

correct is :

"Table 18-4. System Clock Frequency Values".

ARM_CLK_ROOT Default Frequency was 792MHz.

RM has not typo, probably not clear wording, since there is one

document Reference Manual for all I.MX6DQ speed grades.

That is RM is document describing silicon, while speed grades

are selected silicon samples during PVTC testing on factory.

So "18.3 CCM Clock Tree" in IMX6DQRM_Rev.2 description:

"The default frequency values (in MHz) for the PLLs and PFDs is the maximum allowed frequency.

applies to all speed grades - value "792MHz" defined by lowest speed grade:

IMX6DQIEC  Industrial max.800MHz

Best regards

igor

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[keitanagashima]

Dear Igor,

Hello.

Thank you for your prompt reply!

I understood for ARM clock.

I checked another PLLs value and found typo.

PLL4 and PLL5 looked 650MHz from 10.3.2.3 PLLs in MCIMX6DQRM(Rev.2).

But, there were description of PLL4 and PLL5 = 630MHz in "Figure 18-2. Clock Tree".

Is this typo?

And, is there another typo in Figure 18-2?

Best Regards,

Keita

[igorpadykov]

Hi Keita

please create new Community thread

for new questions.

Thanks and Best regards

igor