Masking MIPI CSI MASK1 register & MIPI CSI CRC Calculation

[shajinas]

Hello,

I am working on a custom platform which is based on i.MX6Q + Xilinx Artix7. I'm using android Kitkat KK4.4.3 from Freescale. In the custom platform the Artix-7 FPGA acts as a MIPI CSI Transmitter, which keeps sending color bar data(YUV422) @720p 30fps, 200MHz (Discontinuous)  to i.MX6Q. we tried to capture frame, but we noticed the MIPI_CSI_ERR1 register being set to 0x01001000. Based on the register description it is known that the CRC error is detected.

I have a couple of questions regarding Masking MIPI_CSI_MASK1 register and CRC Calculation

1) I tried masking those two error bits in MIPI_CSI_MASK1 register as shown below. However, I could see the MIPI_CSI_ERR1 bits are set to 0x01001000. On reboot also we are noticing the err bits are set.

How could i mask those error bits ? Is that anything i'm missing in my code ?

diff --git a/drivers/mxc/mipi/mxc_mipi_csi2.c b/drivers/mxc/mipi/mxc_mipi_csi2.c

index df45c36..de7dffc 100644

--- a/drivers/mxc/mipi/mxc_mipi_csi2.c

+++ b/drivers/mxc/mipi/mxc_mipi_csi2.c

@@ -291,8 +292,10 @@ int mipi_csi2_reset(struct mipi_csi2_info *info)

        mipi_csi2_write(info, 0x00010044, MIPI_CSI2_PHY_TST_CTRL1);

        mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

        mipi_csi2_write(info, 0x00000014, MIPI_CSI2_PHY_TST_CTRL1);

        mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);

        mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

+       mipi_csi2_write(info, 0x01001000, MIPI_CSI2_MASK1);

        mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_PHY_SHUTDOWNZ);

2) My MIPI CSI Knowledge is very minimum. Please correct me if i was wrong. Based on my understanding, Every MIPI Packet will have a 16bits CRC field at packet footer. As shown in the Figure 2, Some MIPI CSI Transceiver wll process the first CRC byte as LSB and then the MSB. Does i.MX6 MIPI CSI will also expects the same format or the reverse ?

                                                  FIg 1 : MIPI CSI Packet structure

                                                  FIg 2 : Packet Data and Packet Footer

3) As a question of curiosity, How CRC is calculated for MIPI CSI Packets ?

It would be helpful if you can share your thoughts for these questions. Thanks for your time.

Thanks

Shajin

[igorpadykov]

Hi Shajin

1. MIPI_CSI_MASK1 register masks interrupts, it does not disable crc check

2. i.MX6 MIPI CSI uses this format, as defined in the MIPI CSI-2 Specification

3. MIPI CSI-2 Specification describes crc calculations, the generator polynomial is x16+x12+x5+x0

Best regards

igor

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[shajinas]

Hi Igor,

Thank you very much for the your response.

I would like to understand, If CRC Fails for the incoming Payload data, Whether it will discard the payload or still is it possible to dump the data to Memory ?

If it is possible to dump the data, please provide some pointers for capturing the data.

Regards

Shajin