MMP0F100 failure modes

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MMP0F100 failure modes

433件の閲覧回数
stevelandas
Contributor I

Hi, I am looking at the mmpf0100 from a failure modes point of view. For example, we configure SW2 for 3.3V which is the maximum output for this regulator. Is there a failure mode that would allow this output to exceed 3.3V + the normal tolerance? Also, what is the VREF voltage that the DAC's are using for reference?

Thanks

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380件の閲覧回数
art
NXP Employee
NXP Employee

1. The worst case failure mode of a switching regulator is the short-break of the upper output driver FET, that may cause the output of a switching regulator to become directly connected to VIN. However, this situation is almost unachievable, since there is a number of protection features. First, each switching regulator has the programmable current limiter. Then, the whole chip has the thermal protection circuit that shuts it down in case of excessive overheating.

2. The Vref voltage for the regulator's voltage comparators is generated internally to the chip.


Have a great day,
Artur

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380件の閲覧回数
stevelandas
Contributor I

Thanks Art!

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