I have a custom MIPI-CSI2 device implemented with FPGA and this passive TX PHY design( https://www.altera.com/en_US/pdfs/literature/an/an754.pdf )
This is a single lane device, transmitting 32bit user-defined datatype (type 0x30, virtual channel 0).
The MIPI-CSI clock is 160MHz and 320Mbps.
I set DPHY clock to // 150-160MHz :0x04 //159Mhz.
In my kernel driver, after mipi_csi2_reset(); the DPHY status is 0x610, but after turning on the FPGA, the DPHY status starts switching between 0x000 and 0x010.
According to 40.6.6 of the IMX6DQRM, 0x610 means:
1) "Clock Lane in Stop state
2) "Clock Lane module has NOT entered the Ultra Low Power state" (Not very sure about this one)
3) "Data Lane 0 in Stop state"
I've done some research, and I believe if the DPHY is operating normally, the status should be 0x310/0x300, is this correct?
I see on the scope that the CSI_CLK_HS_P and CSI_CLK_HS_N are both abour 100mV p-p, is this too low?
What have I missed that can cause DPHY not detecting MIPI-CSI DDR clock?
Hi Dehuan
MIPI_CSI_PHY_STATE bits 8 and 9 must be 1 (0x300) and bits 4~7 will
toggle according to the moment you read the register and the state of the transmission,
as stated on document Debug steps for customer MIPI sensor
https://community.freescale.com/docs/DOC-94312
Best regards
igor
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I understand that bit 8 (phy_rxclkactivehs) is low when MIPI DDR clock is not received, so this indicates a problem of the transmit lines or the camera side PHY.
But I don't know what could cause bit 9 (phy_rxulpsclknot) to go 0 (from 0x610 to 0x010)?
Can you explain what bit 9 (phy_rxulpsclknot) indicates when it's 0?
phy_rxulpsclknot - signal indicates that the Clock Lane module has entered the Ultra Low Power state,
please refer to MIPI-CSI2 specification for its description.