We are using a lattice FPGA to send a video data stream to the iMX8Mmini.
We have no embedded TRS codes in the data and no external Vsync signal.
We get SOF interrupts but I don't know what triggers them? Anyone have any idea?
LAST_DMA_REQ_SEL – this is set to 0 in our system (fifo_full_level < hburst_length)
but we are not sure what this text in the manual means, hburst = line length or DMA burst size or something else? Any idea?
The frames sent and then ones displayed are not aligning. We see a shift to the right of the video. This is caused by extra data being written into the very first frame buffer write (the image is stable other than this). The first two frames are skipped (as set by the mask_option bits in CR18) but it seems that these two frames are not cleared and some data from the end of the last frame gets into the FB which then gives this offset (as all lines are shifted right by the data).
Simulation in the FPGA shows that we are not sending extra data and the image is stable other than the fixed shift.
Anyone have any idea what might be causing the frame misalignment in the first frame.
We see this issue with 1080p30 but not 720p60.
Register setup attached
