We are using a lattice FPGA to send a video data stream to the iMX8Mmini.
We have no embedded TRS codes in the data and no external Vsync signal.
We get SOF interrupts but I don't know what triggers them? Anyone have any idea?
LAST_DMA_REQ_SEL – this is set to 0 in our system (fifo_full_level < hburst_length)
but we are not sure what this text in the manual means, hburst = line length or DMA burst size or something else? Any idea?
We can receive PAL format video and deinterlace it.
But NTSC frame size does not work. We get base address switching errors and the DMA does not seem to complete before the CSI bridge sees a new start of frame data. We don't know how the CSI bridge determines when there is new start of frame data.
We have tried changing the size of the video frame that triggers the end of DMA but this does not help.
Anyone have any idea what might be causing the issue?
Or can send register setup for a working NTSC format video...
